Conferences in DBLP
Sinan Kaptanoglu , Greg Bakker , Arun Kundu , Ivan Corneillet , Ben Ting A New High Density and Very Low Cost Reprogrammable FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Heile , Andrew Leaver Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Om Agrawal , Herman Chang , Brad Sharpe-Geisler , Nick Schmitz , Bai Nguyen , Jack Wong , Giap Tran , Fabiano Fontana , Bill Harding An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Chang Wu , Yuzheng Ding Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Marquardt , Vaughn Betz , Jonathan Rose Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Emmert , Dinesh Bhatia A Methodology for Fast FPGA Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Vaughn Betz , Jonathan Rose FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. [Citation Graph (0, 0)][DBLP ] Conf ] André DeHon Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). [Citation Graph (0, 0)][DBLP ] Conf ] S. R. Park , Wayne Burleson Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Li , Scott Hauck Don't Care Discovery for FPGA Configuration Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Emeka Mosanya , Eduardo Sanchez A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Andy Gean Ye , David M. Lewis Procedural Texture Mapping on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , George Varghese , John Wawrzynek , André DeHon HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Marshall , Tony Stansfield , Igor Kostarnov , Jean Vuillemin , Brad L. Hutchings A Reconfigurable Arithmetic Array for Multimedia Application. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey A. Jacob , Paul Chow Memory Interfacing and Instruction Specification for Reconfigurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yaska Sankar , Jonathan Rose Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , N. Ranganathan Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Huiqun Liu , D. F. Wong Circuit Partitioning for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Budiu , Seth Copen Goldstein Fast Compilation for Pipelined Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Deepali Deshpande , Arun K. Somani , Akhilesh Tyagi Configuration Caching Vs Data Caching for Striped FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Reetinder P. S. Sidhu , Alessandro Mei , Viktor K. Prasanna String Natching on Nulticontext FPGAs Using Self-Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] P. Kollig , Bashir M. Al-Hashimi Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Karlheinz Weiß , Thorsten Steckstor , Gernot Koch , Wolfgang Rosenstiel Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System. [Citation Graph (0, 0)][DBLP ] Conf ] Bernie New , Peter Alfke 400-MHz Frequency Counter: A Case Study in Semi-Synchronous Design. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Kornmesser , Torsten Kuberka , Andreas Kugel , Reinhard Männer , Stephan Rühl , M. Sessler , Holger Singpiel ATLANTIS - A Hybrid Approach Combining the Power of FPGA and RISC Processors Based on CompactPCI. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Carro Architecture Considerations for Mixed Signals FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] C. Hart Poskar , Peter J. Czezowski , Robert D. McLeod A Computational Intelligence Based Coarse-Grained Reconfigurable Element. [Citation Graph (0, 0)][DBLP ] Conf ] Hagen Ploog , Tino Rachui , Dirk Timmermann Design Issues in the Development of a JAVA-Processor for Small Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mouna Nakkar , David G. Bentlage , John Harding , David Schwartz , Paul D. Franzon , Thomas M. Conte Dynamically Programmable Cache Evaluation and Virtualization. [Citation Graph (0, 0)][DBLP ] Conf ] Byoungil Jeong , Sungjoo Yoo , Kiyoung Choi Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit Extra-Dimensional Island-Style FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Enrica Filippi , A. Montanaro , M. Paolini , M. Turolla FPGA Design Experiences Using the CSELT VIP (TM) Library. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , J. Fonseca , Ricardo Sal Monteiro , Arnaldo Oliveira , Andreia Melo , Nuno Lau , Konstantin Kondratjuk , Iouliia Skliarova , P. Neves , António de Brito Ferrari FPGA-Targeted Development System for Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] A. Lecerf , F. Vachon , D. Ouellet , Miguel Arias-Estrada FPGA Based Computer Vision Camera. [Citation Graph (0, 0)][DBLP ] Conf ] M. Anand , Sanjiv Kapoor , M. Balakrishnan Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Dick High-Performance 2-D FPGA DCTs Using Polynomial Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] L. Naviner , Jean-Luc Danger , C. Laurent High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijun Yang , Felipe M. G. França Implementing an Artificial CPG Using Fine-Grain FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] James Hwang , Cameron Patterson , Sujoy Mitra Hierarchical Placement Directives for Parametric IP Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] John McCluskey High Speed Calculation of Cyclic Redundancy Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Kun-Ming Ho , Allen C.-H. Wu Module Generation of High Performance FPGA-Based Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Helena Krupnova , Gabriele Saucier Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Akihiro Matsuura , Hidehisa Nagano , Akira Nagoya A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Soulard Prototyping Board and Development Environment for Rapid Prototyping of Real Time and Regular Digital Signal Processing Application. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Guccione , Delon Levi Run-Time Parameterizable Cores. [Citation Graph (0, 0)][DBLP ] Conf ] John McCluskey Practical Applications of Recursive VHDL Components in FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Matti Tommiska Special Arithmetic Operations on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , A. L. Burress Self-Checking Logic Design for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Vinoo Srinivasan , Ranga Vemuri Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Guang-Ming Wu , Michael Shyu , Yao-Wen Chang Universal Switch Blocks for Three-Dimensional FPGA Design. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Koch Unified Access to Heterogeneous Module Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Florent de Dinechin , Wayne Luk , Steve McKeever Towards Adaptable Hierarchical Placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Murooka , Atsushi Takahara , Toshiaki Miyazaki Why a CAD-Verified FPGA Makes Routing so Simple and Fast! A Result of Co-Designing FPGAs and CAD Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Luis Nunez , Claudia Feregrino , Stephen Bateman , Simon Jones The X-MatchLITE FPGA-Based Data Compressor. [Citation Graph (0, 0)][DBLP ] Conf ] 