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Conferences in DBLP
- K. K. Lee, D. F. Wong
LRoute: a delay minimal router for hierarchical CPLDs. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:12-20 [Conf]
- Steven J. E. Wilton
A crosstalk-aware timing-driven router for FPGAs. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:21-28 [Conf]
- Chandra Mulpuri, Scott Hauck
Runtime and quality tradeoffs in FPGA placement and routing. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:29-36 [Conf]
- Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:39-47 [Conf]
- Gang Chen, Jason Cong
Simultaneous logic decomposition with technology mapping in FPGA designs. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:48-55 [Conf]
- Guy G. Lemieux, David M. Lewis
Using sparse crossbars within LUT. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:59-68 [Conf]
- Peter Hallschmid, Steven J. E. Wilton
Detailed routing architectures for embedded programmable logic IP cores. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:69-74 [Conf]
- Mike Sheng, Jonathan Rose
Mixing buffers and pass transistors in FPGA routing architectures. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:75-84 [Conf]
- John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor
Reprogrammable network packet processing on the field programmable port extender (FPX). [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:87-93 [Conf]
- Pawel Chodowiec, Po Khuon, Kris Gaj
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:94-102 [Conf]
- Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:103-110 [Conf]
- Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta
Is marriage in the cards for programmable logic, microprocessors and ASICs? [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:111- [Conf]
- Greg Snider, Barry Shackleford, Richard J. Carter
Attacking the semantic gap between application programming languages and configurable hardware. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:115-124 [Conf]
- Pablo Moisset, Pedro C. Diniz, Joonseok Park
Matching and searching analysis for parallel hardware implementation on FPGAs. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:125-133 [Conf]
- Janette Frigo, Maya Gokhale, Dominique Lavenier
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:134-140 [Conf]
- Jorge E. Carrillo, Paul Chow
The effect of reconfigurable units in superscalar processors. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:141-150 [Conf]
- Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
Interconnect pipelining in a throughput-intensive FPGA architecture. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:153-160 [Conf]
- Deshanand P. Singh, Stephen Dean Brown
The case for registered routing switches in field programmable gate arrays. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:161-169 [Conf]
- Andreas Dandalis, Viktor K. Prasanna
Configuration compression for FPGA-based embedded systems. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:173-182 [Conf]
- Wei-Je Huang, Edward J. McCluskey
A memory coherence technique for online transient error recovery of FPGA configurations. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:183-192 [Conf]
- Prasanna Sundararajan, Steve Guccione
Run-Time defect tolerance using JBits. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:193-198 [Conf]
- Jörg Ritter, Paul Molitor
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:201-206 [Conf]
- Gerhard Lienhart, Reinhard Männer, K. H. Noffz, R. Lay
An FPGA-based video compressor for H.263 compatible bit streams. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:207-212 [Conf]
- S. Ramachandran, S. Srinivasan
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. [Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:213-219 [Conf]
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