The SCEAS System
Navigation Menu

Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
2001 (conf/fpga/2001)

  1. K. K. Lee, D. F. Wong
    LRoute: a delay minimal router for hierarchical CPLDs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:12-20 [Conf]
  2. Steven J. E. Wilton
    A crosstalk-aware timing-driven router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:21-28 [Conf]
  3. Chandra Mulpuri, Scott Hauck
    Runtime and quality tradeoffs in FPGA placement and routing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:29-36 [Conf]
  4. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:39-47 [Conf]
  5. Gang Chen, Jason Cong
    Simultaneous logic decomposition with technology mapping in FPGA designs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:48-55 [Conf]
  6. Guy G. Lemieux, David M. Lewis
    Using sparse crossbars within LUT. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:59-68 [Conf]
  7. Peter Hallschmid, Steven J. E. Wilton
    Detailed routing architectures for embedded programmable logic IP cores. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:69-74 [Conf]
  8. Mike Sheng, Jonathan Rose
    Mixing buffers and pass transistors in FPGA routing architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:75-84 [Conf]
  9. John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor
    Reprogrammable network packet processing on the field programmable port extender (FPX). [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:87-93 [Conf]
  10. Pawel Chodowiec, Po Khuon, Kris Gaj
    Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:94-102 [Conf]
  11. Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski
    Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:103-110 [Conf]
  12. Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta
    Is marriage in the cards for programmable logic, microprocessors and ASICs? [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:111- [Conf]
  13. Greg Snider, Barry Shackleford, Richard J. Carter
    Attacking the semantic gap between application programming languages and configurable hardware. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:115-124 [Conf]
  14. Pablo Moisset, Pedro C. Diniz, Joonseok Park
    Matching and searching analysis for parallel hardware implementation on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:125-133 [Conf]
  15. Janette Frigo, Maya Gokhale, Dominique Lavenier
    Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:134-140 [Conf]
  16. Jorge E. Carrillo, Paul Chow
    The effect of reconfigurable units in superscalar processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:141-150 [Conf]
  17. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Interconnect pipelining in a throughput-intensive FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:153-160 [Conf]
  18. Deshanand P. Singh, Stephen Dean Brown
    The case for registered routing switches in field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:161-169 [Conf]
  19. Andreas Dandalis, Viktor K. Prasanna
    Configuration compression for FPGA-based embedded systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:173-182 [Conf]
  20. Wei-Je Huang, Edward J. McCluskey
    A memory coherence technique for online transient error recovery of FPGA configurations. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:183-192 [Conf]
  21. Prasanna Sundararajan, Steve Guccione
    Run-Time defect tolerance using JBits. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:193-198 [Conf]
  22. Jörg Ritter, Paul Molitor
    A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:201-206 [Conf]
  23. Gerhard Lienhart, Reinhard Männer, K. H. Noffz, R. Lay
    An FPGA-based video compressor for H.263 compatible bit streams. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:207-212 [Conf]
  24. S. Ramachandran, S. Srinivasan
    FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:213-219 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002