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Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
1995 (conf/fpga/95)

  1. Shashidhar Thakur, D. F. Wong
    On Designing ULM-based FPGA Logic Modules. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:3-9 [Conf]
  2. Vaughn Betz, Jonathan Rose
    Using Architectural ``Families'' to Increase FPGA Speed and Density. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:10-16 [Conf]
  3. Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai
    Design of FPGAs with Area I/O for Field Programmable MCM. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:17-23 [Conf]
  4. Charles Selvidge, Anant Agarwal, Matthew Dahl, Jonathan Babb
    TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:25-31 [Conf]
  5. Scott Hauck, Gaetano Borriello
    Logic Partition Orderings for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:32-38 [Conf]
  6. H. Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein, L. R. Mullin, R. Ziegler
    Hardware Assists for High Performance Computing Using a Mathematics of Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:39-45 [Conf]
  7. Laurent Moll, Jean Vuillemin, Philippe Boucard
    High-Energy Physics on DECPeRLe-1 Programmable Active Memory. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:47-52 [Conf]
  8. Stephen D. Scott, Ashok Samal, Sharad C. Seth
    HGA: A Hardware-Based Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:53-59 [Conf]
  9. Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois
    The Design of RPM: An FPGA-based Multiprocessor Emulator. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:60-66 [Conf]
  10. Jason Cong, Yean-Yow Hwang
    Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:68-74 [Conf]
  11. Baher Haroun, Behzad Sajjadi
    Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:75-81 [Conf]
  12. Jason Cong, Yuzheng Ding
    On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:82-88 [Conf]
  13. Nam Sung Woo
    Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:90-96 [Conf]
  14. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Architecture of Centralized Field-Configurable Memory. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:97-103 [Conf]
  15. P. Glenn Gulak, Paul Chow
    A Field-Programmable Mixed-Analog-Digital Array. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:104-109 [Conf]
  16. Larry McMurchie, Carl Ebeling
    PathFinder: A Negotiation-based Performance-driven Router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:111-117 [Conf]
  17. Anmol Mathur, K. C. Chen, C. L. Liu
    Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:118-124 [Conf]
  18. Tong Liu, Wei-Kang Huang, Fabrizio Lombardi
    Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:125-131 [Conf]
  19. Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
    Spectral-Based Multi-Way FPGA Partitioning. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:133-139 [Conf]
  20. Dennis J.-H. Huang, Andrew B. Kahng
    Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:140-145 [Conf]
  21. Kalapi Roy-Neogi, Carl Sechen
    Multiple FPGA Partitioning with Performance Optimization. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:146-152 [Conf]
  22. Brian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain
    Techniques for FPGA Implementation of Video Compression Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:154-159 [Conf]
  23. H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
    An SBus Monitor Board. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:160-166 [Conf]
  24. Tsuyoshi Isshiki, Wayne Wei-Ming Dai
    High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:167-173 [Conf]
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