Conferences in DBLP
Elias Ahmed , Jonathan Rose The effect of LUT and cluster size on deep-submicron FPGA performance and density. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Heile , Andrew Leaver , Kerry Veenstra Programmable memory blocks supporting content-addressable memory. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Singh , Luca Macchiarulo , Arindam Mukherjee , Malgorzata Marek-Sadowska A novel high throughput reconfigurable FPGA architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Adam J. Elbirt , Christof Paar An FPGA implementation and performance evaluation of the Serpent block cipher. [Citation Graph (0, 0)][DBLP ] Conf ] Hea Joung Kim , William H. Mangione-Smith Factoring large numbers with programmable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Hui Huang , Xin Yuan Technology mapping for k/m-macrocell based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Kaviani , Stephen Dean Brown Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. E. Wilton Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Kenneth Yan Synthesis for FPGAs with embedded memory blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Hue-Sung Kim , Arun K. Somani , Akhilesh Tyagi A reconfigurable multi-function computing cache architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Zhi Alex Ye , Nagaraj Shenoy , Prithviraj Banerjee A C compiler for a processor with a reconfigurable functional unit. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit , Ray Andraka , Philip Friedin , Satnam Singh , Tim Southgate The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers. [Citation Graph (0, 0)][DBLP ] Conf ] Lorenz Huelsbergen A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Moritoshi Yasunaga , Jung Hwan Kim , Ikuo Yoshihara The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. [Citation Graph (0, 0)][DBLP ] Conf ] S. Kumar , Luiz Pires , Subburajan Ponnuswamy , C. Nanavati , J. Golusky , M. Vojta , S. Wadi , D. Pandalai , Henk A. E. Spaanenburg A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Lockwood , Jonathan S. Turner , David E. Taylor Field programmable port extender (FPX) for distributed routing and queuing. [Citation Graph (0, 0)][DBLP ] Conf ] Ali M. Shankiti , Miriam Leeser Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. [Citation Graph (0, 0)][DBLP ] Conf ] Guy G. Lemieux , Paul Leventis , David M. Lewis Generating highly-routable sparse crossbars for PLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Pak K. Chan , Martine D. F. Schlag New parallelization and convergence results for NC: a negotiation-based FPGA router. [Citation Graph (0, 0)][DBLP ] Conf ] Vaughn Betz , Jonathan Rose Automatic generation of FPGA routing architectures from high-level descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Lakamraju , Russell Tessier Tolerating operational faults in cluster-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Karlheinz Weiß , Carsten Oetker , Igor Katchan , Thorsten Steckstor , Wolfgang Rosenstiel Power estimation approach for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Marquardt , Vaughn Betz , Jonathan Rose Timing-driven placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hyuk-Jun Lee , Michael J. Flynn Coarse-grained carry architecture for FPGA (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Chung Lin , Su-Feng Tseng , Tsai-Ming Hsieh Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Eric K. Pauer , Paul D. Fiore , John M. Smith , Cory S. Myers Algorithm analysis and mapping environment for adaptive computing systems (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] V. S. Balakrishnan , Hardy J. Pottinger , Fikret Erçal , Mukesh Agarwal Design and implementation of an FPGA based processor for compressed images (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Cesare Alippi , William Fornaciari , Laura Pozzi , Mariagiovanna Sami Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Barry Shackleford , Etsuko Okushi , Mitsuhiro Yasuda , Hisao Koizumi , Katsuhiko Seo , Takashi Iwamoto , Hiroto Yasuura An FPGA-based genetic algorithm machine (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Ian Brynjolfson , Zeljko Zilic FPGA clock management for low power applications (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] F. S. Ogrenci , Aggelos K. Katsaggelos , Majid Sarrafzadeh FPGA implementation and analysis of image restoration. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Wirthlin , Paul Graham Improving the performance and efficiency of an adaptive amplification operation using configurable hardware (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Piyush Jamkhandi , Amar Mukherjee , Kunal Mukherjee , Robert Franceschini Novel hardware-software architecture for the recursive merge filtering algorithm (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Andrés D. García , Jean-Luc Danger , Wayne P. Burleson Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit , David Whelihan , Peter Kamarchik , Frank Gennari Scalable interconnect and power distribution for island-style FPGAs (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Gábor Szedö , Sandeep Neema , Jason Scott , Ted Bapty Reconfigurable target recognition system (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Rob McCready , Jonathan Rose Real-time, frame-rate face detection on a configurable hardware system (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Abdelkrim Kamel Oudjida , Sabrina Titri , Mustapha Hamarlain Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] William Fornaciari , Vincenzo Piuri , Luigi Ripamonti Virtualization of FPGA via segmentation (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Michael Herz , Thomas Hoffmann , Ulrich Nageldinger Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). [Citation Graph (0, 0)][DBLP ] Conf ] 