Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
1997 (conf/fpga/97)

1. Steven Trimberger, Khue Duong, Bob Conn
   Architecture Issues and Solutions for a High-Capacity FPGA. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:3-9 [Conf]
   
2. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
   Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:10-16 [Conf]
   
3. Glenn H. Chapman, Benoit Dufort
   Laser Correcting Defects to Create Transparent Routing for Large Area FPGA's. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:17-23 [Conf]
   
4. Frank Vahid
   I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:27-34 [Conf]
   
5. Jason Cong, Yean-Yow Hwang
   Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:35-42 [Conf]
   
6. Amit Chowdhary, John P. Hayes
   General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:43-49 [Conf]
   
7. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
   The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:53-61 [Conf]
   
8. Brian Von Herzen
   Signal Processing at 250 MHz Using High-Performance FPGA's. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:62-68 [Conf]
   
9. Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
   Module Generation of Complex Macros for Logic-Emulation Applications. [Citation Graph (0, 0)][DBLP]
   FPGA, 1997, pp:69-75 [Conf]
   
10. Ray A. Bittner, Peter M. Athanas
    Wormhole Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:79-85 [Conf]
    
11. Michael J. Wirthlin, Brad L. Hutchings
    Improving Functional Density Through Run-Time Constant Propagation. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:86-92 [Conf]
    
12. Akihiro Tsutsui, Toshiaki Miyazaki
    YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:93-100 [Conf]
    
13. Herman Schmit
    Is Reconfigurable Computing Commercially Viable (panel)? [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:101- [Conf]
    
14. Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
    Synthesis and Floorplanning for Large Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:105-111 [Conf]
    
15. Jianzhong Shi, Dinesh Bhatia
    Performance Driven Floorplanning for FPGA Based Designs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:112-118 [Conf]
    
16. R. Glenn Wood, Rob A. Rutenbar
    FPGA Routing and Routability Estimation via Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:119-125 [Conf]
    
17. Jonathan Rose, Dwight D. Hill
    Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:129-132 [Conf]
    
18. Kurt Keutzer
    Challenges in CAD for the One Million Gate FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:133-134 [Conf]
    
19. C. A. Looby, Colin Lyden
    A CMOS Continuous-Time Field Programmable Analog Array. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:137-141 [Conf]
    
20. Douglas Chang, Malgorzata Marek-Sadowska
    Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:142-148 [Conf]
    
21. Michael D. Hutton, Jonathan Rose, Derek G. Corneil
    Generation of Synthetic Sequential Benchmark Circuits. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:149-155 [Conf]
    
22. Alexandre F. Tenca, Milos D. Ercegovac
    Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:159-165 [Conf]
    
23. Monica Alderighi, E. L. Gummati, Vincenzo Piuri, Giacomo R. Sechi
    A FPGA-Based Implementation of a Fault-Tolerant Neural Architecture for Photon Identification. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:166-172 [Conf]