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Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
2002 (conf/fpga/2002)

  1. Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev
    Interconnect enhancements for a high-speed PLD architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:3-10 [Conf]
  2. Herman Schmit, Vikas Chandra
    FPGA switch block layout and evaluation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:11-18 [Conf]
  3. Guy G. Lemieux, David M. Lewis
    Circuit design of routing switches. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:19-28 [Conf]
  4. Radhika S. Grover, Weijia Shang, Qiang Li
    A faster distributed arithmetic architecture for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:31-39 [Conf]
  5. Alan Daly, William P. Marnane
    Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:40-49 [Conf]
  6. J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier
    A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:50-55 [Conf]
  7. Amit Singh, Malgorzata Marek-Sadowska
    Efficient circuit clustering for area and power reduction in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:59-66 [Conf]
  8. Deshanand P. Singh, Stephen Dean Brown
    Integrated retiming and placement for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:67-76 [Conf]
  9. Jason Cong, Yizhou Lin, Wangning Long
    SPFD-based global rewiring. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:77-84 [Conf]
  10. William Chow, Jonathan Rose
    EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:85-94 [Conf]
  11. Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski
    Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:97-105 [Conf]
  12. Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider
    FPGA implementation of neighborhood-of-four cellular automata random number generators. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:106-112 [Conf]
  13. Tom Kean
    Cryptographic rights management of FPGA intellectual property cores. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:113-118 [Conf]
  14. Deshanand P. Singh, Stephen Dean Brown
    Constrained clock shifting for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:121-126 [Conf]
  15. Ian Robertson, James Irvine, Patrick Lysaght, David Robinson
    Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:127-135 [Conf]
  16. Stuart McCracken, Zeljko Zilic
    FPGA test time reduction through a novel interconnect testing scheme. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:136-144 [Conf]
  17. Andy Yan, Rebecca Cheng, Steven J. E. Wilton
    On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:147-156 [Conf]
  18. Li Shang, Alireza Kaviani, Kusuma Bathala
    Dynamic power consumption in Virtex[tm]-II FPGA family. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:157-164 [Conf]
  19. Shawn Phillips, Scott Hauck
    Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:165-173 [Conf]
  20. Greg Snider
    Performance-constrained pipelining of software loops onto reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:177-186 [Conf]
  21. Zhiyuan Li, Scott Hauck
    Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:187-195 [Conf]
  22. Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
    Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:196-205 [Conf]
  23. K. K. Lee, D. F. Wong
    Incremental reconfiguration of multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:206-213 [Conf]
  24. Srdjan Coric, Miriam Leeser, Eric Miller, Marc Trepanier
    Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:217-226 [Conf]
  25. Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson
    A dynamically reconfigurable adaptive viterbi decoder. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:227-236 [Conf]
  26. Pedro C. Diniz, Joonseok Park
    Data reorganization engines for the next generation of system-on-a-chip FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:237-244 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002