Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
1996 (conf/fpga/96)

1. Alireza Kaviani, Stephen Dean Brown
   Hybrid FPGA Architecture. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:3-9 [Conf]
   
2. Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider, Lyle Albertson
   Plasma: An FPGA for Million Gate Systems. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:10-16 [Conf]
   
3. Kengo Azegami, Shoichiro Kashiwakura, Koichi Yamashita
   Flexible FPGA Architecture Realized of General Purpose SOG. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:17-22 [Conf]
   
4. Zeljko Zilic, Zvonko G. Vranesic
   Using BDDs to Design ULMs for FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:24-30 [Conf]
   
5. Shashidhar Thakur, D. F. Wong
   Universal Logic Modules for Series-Parallel Functions. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:31-37 [Conf]
   
6. E. Schubert, Wolfgang Rosenstiel
   Combined Spectral Techniques for Boolean Matching. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:38-43 [Conf]
   
7. Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses
   The Wave Pipeline Effect on LUT-Based FPGA Architectures. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:45-50 [Conf]
   
8. Vi Cuong Chan, David M. Lewis
   Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:51-57 [Conf]
   
9. Peichen Pan, C. L. Liu
   Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:58-64 [Conf]
   
10. Joel Darnauer, Wayne Wei-Ming Dai
    A Method for Generating Random Circuits and Its Application to Routability Measurement. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:66-72 [Conf]
    
11. André DeHon
    Entropy, Counting, and Programmable Interconnect. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:73-79 [Conf]
    
12. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Universal Switch-Module Design for Symmetric-Array-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:80-86 [Conf]
    
13. Adrian Bratt, Ian Macbeth
    Design and Implementation of a Field Programmable Analogue Array. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:88-93 [Conf]
    
14. Hans W. Klein
    The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:94-98 [Conf]
    
15. Fabrizio Lombardi, David Ashen, Xiao-Tao Chen, Wei-Kang Huang
    Diagnosing Programmable Interconnect Systems for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:100-106 [Conf]
    
16. Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici
    Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:107-113 [Conf]
    
17. André DeHon
    DPGA Utilization and Application. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:115-121 [Conf]
    
18. Michael J. Wirthlin, Brad L. Hutchings
    Sequencing Run-Time Reconfigured Hardware with Software. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:122-128 [Conf]
    
19. Chris Dick
    Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:129-135 [Conf]
    
20. Jason Cong, John Peck, Yuzheng Ding
    RASP: A General Logic Synthesis System for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:137-143 [Conf]
    
21. Darren C. Cronquist, Larry McMurchie
    Emerald: An Architecture-Driven Tool Compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:144-150 [Conf]
    
22. Andreas Koch
    Structured Design Implementation: A Strategy for Implementing Regular Datapaths on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:151-157 [Conf]