Conferences in DBLP
Emil S. Ochotta , Patrick J. Crotty , Charles R. Erickson , Chih-Tsung Huang , Rajeev Jayaraman , Richard C. Li , Joseph D. Linoff , Luan Ngo , Hy V. Nguyen , Kerry M. Pierce , Douglas P. Wieland , Jennifer Zhuang , Scott S. Nance A Novel Predictable Segmented FPGA Routing Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Takahara , Toshiaki Miyazaki , Takahiro Murooka , Masaru Katayama , Kazuhiro Hayashi , Akihiro Tsutsui , Takaki Ichimori , Ken-nosuke Fukami More Wires and Fewer LUTs: A Design Methodology for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kerry Veenstra , Bruce Pedersen , Jay Schleicher , Chiakang Sung Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yean-Yow Hwang Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , Chih-Chang Lin A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed A. S. Khalid , Jonathan Rose A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Srihari Cadambi , Jeffrey Weener , Seth Copen Goldstein , Herman Schmit , Donald E. Thomas Managing Pipeline-Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hauck Configuration Prefetch for Single Context Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Huiqun Liu , Kai Zhu , D. F. Wong Circuit Partitioning with Complex Resource Constraints in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] S. A. Senouci , A. Amoura , Helena Krupnova , Gabriele Saucier Timing Driven Floorplanning on Programmable Hierarchical Targets. [Citation Graph (0, 0)][DBLP ] Conf ] Lan Zhao , D. M. H. Walker , Fabrizio Lombardi Bridging Fault Detection in FPGA Interconnects Using IDDQ . [Citation Graph (0, 0)][DBLP ] Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Efficiently Supporting Fault-Tolerance in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Rose , Sinan Kaptanoglu , Clive McCarthy , Rob Smith , Sandip Vij , Steve Taylor Constraints from Hell: How to Tell Makes a Good FPGA (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Callahan , Philip Chong , André DeHon , John Wawrzynek Fast Module Mapping and Placement for Datapaths in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan W. Gehring , Stefan H.-M. Ludwig Fast Integrated Tools for Circuit Design with FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jordan S. Swartz , Vaughn Betz , Jonathan Rose A Fast Routability-Driven Router for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Trimberger Scheduling Designs into a Time-Multiplexed FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas Chang , Malgorzata Marek-Sadowska Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. E. Wilton SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Songjie Xu Technology Mapping for FPGAs with Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ray Andraka A Survey of CORDIC Algorithms for FPGA Based Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Graham , Brent E. Nelson FPGA-Based Sonar Processing. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Koza , Forrest H. Bennett III , Jeffrey L. Hutchings , Stephen L. Bade , Martin A. Keane , David Andre Evolving Computer Programs Using Rapidly Reconfigurable Field-Programmable Gate Arrays and Genetic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hauck , Matthew M. Hosler , Thomas W. Fry High-Performance Carry Chains for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] James R. Anderson , Siddharth Sheth , Kaushik Roy A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Helge Anderson , Stephen Dean Brown An LPGA with Foldable PLA-style Logic Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Isshiki , Takenobu Shimizugashira , Akihisa Ohta , Imanuddin Amril , Hiroaki Kunieda A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Paul T. Sasaki A Fast FPGA (FFPGA) Using Active Interconnect (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Karlheinz Weiß , Ronny Kistner , Arno Kunzmann , Wolfgang Rosenstiel Advantages of the XC6000 Architecture for Embedded System Design (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Helena Krupnova , B. Behnam , Gabriele Saucier Block and IP Wrapping for Efficient Design on FPGAs (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Silviu M. S. A. Chiricescu , Mankuan Michael Vai Design of a Three-Dimensional FPGA for Reconfigurable Computing Machines (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] David Jefferson , Srinivas Reddy , Christopher Lane , Ninh Ngo , Wanli Chang , Manuel Mijia , Ketan Zaveri , Cameron McClintock , Richard Cliff A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Hanho Lee , Sarvesh Shrivastava , Gerald E. Sobelman FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jo Depreitere , Herwig Van Marck , Jan Van Campenhout GART: A New, Flexible Placement and Routing Tool for Research on FPGA Architectures (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Takenori Kouda , Yahiko Kambayashi FPGA Circuit Optimization Based on Block Integration (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Xue-Jie Zhang , Kam-Wing Ng , Gilbert H. Young High-Level Synthesis Using Genetic Algorithms for Dynamically Reconfigurable FPGAs (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Emeka Mosanya , Jean-Michel Puiatti , Eduardo Sanchez Hardware Implementation of Generalized Profile Search on the GENSTROM Machine (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Walter B. Ligon III , Greg Monn , S. P. McMillan , Kevin Schoonover , Fred Stivers , Keith D. Underwood Implementation of IEEE Single-Precision Floating-Point Operations on FPGAs (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , A. Marshall , Laura Pozzi , Mariagiovanna Sami Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Jimenez , Chin-Long Wey , Michael A. Shanblatt Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Diessel , Hossam A. ElGindy Partial FPGA Rearrangement by Local Repacking (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jeanette F. Arrigo , Kevin J. Page , Paul M. Chau , N. C. Tien Reconfigurable Processing for Robust Navigation and Control (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] A. Mtibaa , M. Abid , R. Tourki Rapid Prototyping of Multi-Recommendation Modem (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Kei Mak , D. F. Wong Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Hidehisa Nagano , Takayuki Suyama , Akira Nagoya Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Miyamori , Kunle Olukotun REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jacques-Olivier Haenni , Erik Bruchez , Emeka Mosanya , Eduardo Sanchez RENCO: A Reconfigurable Network Computer (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jesus Crespo , Juan Carlos Diaz , Pimitivo Matas FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] 