Conferences in DBLP
Mingjie Lin , Abbas El Gamal A routing fabric for monolithically stacked 3D-FPGA. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:3-12 [Conf ] Scott C. Smith Design of a logic element for implementing an asynchronous FPGA. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:13-22 [Conf ] Wenyi Feng , Sinan Kaptanoglu Designing efficient input interconnect blocks for LUT clusters using counting and entropy. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:23-32 [Conf ] Steven J. E. Wilton , Chun Hok Ho , Philip Heng Wai Leong , Wayne Luk , Bradley R. Quinton A synthesizable datapath-oriented embedded FPGA fabric. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:33-41 [Conf ] David Slogsnat , Alexander Giese , Ulrich Brüning A versatile, low latency HyperTransport core. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:45-52 [Conf ] Shih-Lien L. Lu , Peter Yiannacouras , Rolf Kassa , Michael Konow , Taeweon Suh An FPGA-based Pentium in a complete desktop system. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:53-59 [Conf ] Edward C. Lin , Kai Yu , Rob A. Rutenbar , Tsuhan Chen A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:60-68 [Conf ] Satish Sivaswamy , Kia Bazargan Variation-aware routing for FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:71-79 [Conf ] Yan Lin , Lei He Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:80-88 [Conf ] Kai Zhu Post-route LUT output polarity selection for timing optimization. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:89-96 [Conf ] Jason Cong , Guoling Han , Wei Jiang Synthesis of an application-specific soft multiprocessor system. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:99-107 [Conf ] Bita Gorjiara , Daniel Gajski FPGA-friendly code compression for horizontal microcoded custom IPs. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:108-115 [Conf ] Sewook Wee , Jared Casper , Njuguna Njoroge , Yuriy Teslyar , Daxia Ge , Christos Kozyrakis , Kunle Olukotun A practical FPGA-based framework for novel CMP research. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:116-125 [Conf ] Mike Wirthlin , Misha Burich , Andrew Guyler , Brian Von Herzen High-level languages: the future or a passing fad? [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:127- [Conf ] Paul Chow , Mike Hutton Integrating FPGAs in high-performance computing: introduction. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:131- [Conf ] Nathan Woods Integrating FPGAs in high-performance computing: the architecture and implementation perspective. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:132- [Conf ] Satnam Singh Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:133-135 [Conf ] Jason Cong , Kirill Minkovich Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:139-147 [Conf ] Kevin Oo Tinmaung , David Howland , Russell Tessier Power-aware FPGA logic synthesis using binary decision diagrams. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:148-155 [Conf ] Julien Lamoureux , Guy G. Lemieux , Steven J. E. Wilton GlitchLess: an active glitch minimization technique for FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:156-165 [Conf ] Yohei Matsumoto , Masakazu Hioki , Takashi Kawanami , Toshiyuki Tsutsumi , Tadashi Nakagawa , Toshihiro Sekigawa , Hanpei Koike Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:169-177 [Conf ] N. Pete Sedcole , Peter Y. K. Cheung Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:178-187 [Conf ] Dirk Koch , Christian Haubelt , Jürgen Teich Efficient hardware checkpointing: concepts, overhead analysis, and implementation. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:188-196 [Conf ] Nicholas Weaver , Vern Paxson , José M. González The shunt: an FPGA-based accelerator for network intrusion prevention. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:199-206 [Conf ] Tim Gueneysu , Christof Paar , Jan Pelzl Attacking elliptic curve cryptosystems with special-purpose hardware. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:207-215 [Conf ] Nathan Jachimiec , Fernando Martinez-Vallin , Jafar Saniie CReconfigurable finite field instruction set architecture. [Citation Graph (0, 0)][DBLP ] FPGA, 2007, pp:216-220 [Conf ]