Conferences in DBLP
Markus Weinhardt Portable Pipeline Synthesis for FCCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Legl , Klaus Eckl , Bernd Wurth Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play? [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Luk , Shaori Guo , Nabeel Shirazi , N. Zhuang A Framework for Developing Parameterised FPGA Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Miyazaki , Akihiro Tsutsui , Kenji Ishii , Naohisa Ohta FACT: Co-evaluation Environment for FPGA Architecture and CAD System. [Citation Graph (0, 0)][DBLP ] Conf ] Jörn Stohmann , Erich Barke A Universal CLA Adder Generator for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichiro Shibata , Xiao-ping Ling , Hideharu Amano An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Jürgen Becker , Rainer Kress Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan H.-M. Ludwig The Design of a Coprocessor Board Using Xilinx's XC6200 FPGA - An Experience Report. [Citation Graph (0, 0)][DBLP ] Conf ] Doug Smith , Dinesh Bhatia RACE: Reconfigurable and Adaptive Computing Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Dick Computing 2-D DFTs Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrike Ober , Hans-Jürgen Herpel , Manfred Glesner CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] David W. Trainor , Roger Woods Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Ebeling , Darren C. Cronquist , Paul Franklin RaPiD - Reconfigurable Pipelined Datapath. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Suyama , Makoto Yokoo , Hiroshi Sawada Solving Satisfiability Problems on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] César Sanz , Laura de Zulueta , Juan M. Meneses FPGA Implementation of the Block-Matching Algorithm for Motion Estimation in Image Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Braun , Jörg Friedrich , Thomas Grün , Josef Lembert Parallel CRC Computation in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Meyer-Bäse Coherent Demodulation with FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan W. Gehring , Stefan H.-M. Ludwig The Trianus System and Its Application to Custom Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Nigel Lester , Jonathan Saul Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form. [Citation Graph (0, 0)][DBLP ] Conf ] Kalle Tammemäe , Mattias O'Nils , Ahmed Hemani Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Keisuke Inoue , Toru Kisuki , Michitaka Okuno , Etsuko Shimizu , Takuya Terasawa , Hideharu Amano ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaj Janzen , Franz J. Rammig A Slow Motion Engine for the Analysis of FPGA-Based Prototypes. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred Hesener Implementing Reconfigurable Datapaths in FPGAs for Adaptive Filter Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Kean , Bernie New , Robert Slous A Fast Constant Coefficient Multiplier for the XC6200. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht Ditzinger , Ralph Remme Key Issues for User Acceptance of FPGA Design Tools. [Citation Graph (0, 0)][DBLP ] Conf ] B. L. Combridge , P. S. Cornfield , S. Naunton Reconfigurable DSP Demonstrators for the Development of Spacecraft Payload Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Casselman Reconfigurable Logic Based Fibre Channel Network Card With Sub 2 Micro-Second Raw Latency. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Haddy , David J. Skellern An Asynchronous Transfer Mode (ATM) Stream Demultiplexer and Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Milan Vasilko , Djamel Ait-Boudaoud Optically Reconfigurable FPGAs: Is this a Future Trend? [Citation Graph (0, 0)][DBLP ] Conf ] Zoran A. Salcic , R. Bruce Maunder CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Milan Vasilko , Djamel Ait-Boudaoud Architectural Synthesis Techniques for Dynamically Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Eggers , Patrick Lysaght , Hugh Dick , Gordon McGregor Fast Reconfigurable Crossbar Switching in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Gulsun Yasar , Julie Devins , Yelena Tsyrkina , Gregg Stadtlander , Eric Millham Growable FPGA Macro Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Paul Heron , Roger Woods Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner A Virtual Hardware Operating System for the Xilinx XC6200. [Citation Graph (0, 0)][DBLP ] Conf ] Andrej Trost , Roman Kuznar , Andrej Zemva , Baldomir Zajc An Experimental Programmable Environment for Prototyping Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gschwind , Christian Mautner Migration from Schematic-Based Designs to a VHDL Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Balboni , Loris Valenti ASIC Design and FPGA Design: A Unified Design Methodology Applied to Different Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Dick , Fred Harris FIR Filtering with FPGAs Using Quadrature Sigma-Delta Modulation Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Kang Yi , Chu Shik Jhon A New FPGA Technology Mapping Approach by Cluster Merging. [Citation Graph (0, 0)][DBLP ] Conf ] L. Larsson An EPLD Based Transient Recorder for Simulation of Video Signal Processing Devices in an VHDL Environment Close to System Level Conditions. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Meyer-Bäse Convolutional Error Decoding with FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Branka Medved Rogina , Karolj Skala , Bozidar Vojnovic Metastability Characteristics Testing for Programmable Logic Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Rowley , Colin Lyden Implementing Sigma Delta Modulator Prototype Designs on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Ruiz , Yago Torroja , José Luis García Design of a VME Parametrized Library for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Schumacher , Bernhard Josko , Gerhard Wagner , Martin Radetzki Development of a Telephone Answering Machine in a Lab - FPGAs in Education. [Citation Graph (0, 0)][DBLP ] Conf ] V. Tchoumatchenko , T. Vassileva , R. Ribas , Alain Guyot FPGA Design Migration: Some Remarks. [Citation Graph (0, 0)][DBLP ] Conf ] Sébastien Pillement , Lionel Torres , Michel Robert , Gaston Cambon Concurrent Design of Hardware/Software Dedicated Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Abdellah Touhafi , Wouter Brissinck , Erik F. Dirkx The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Weinhardt Computing Weight Distributions of Binary Linear Block Codes on a CCM. [Citation Graph (0, 0)][DBLP ] Conf ] 