Conferences in DBLP
Michael Hermann , Wolfgang Hoffmann Fault Modeling and Test Generation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo de Oliveira Duarte , Michael Nicolaidis A Test Methodology Applied to Cellular Logic Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Michal Servít , Zdenek Muzikár Integrated Layout Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Robert , Lionel Torres , Fernando Moraes , Daniel Auvergne Influence of Locig Block Layout Architecture on FPGA Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Ismail Haritaoglu , Cevdet Aykanat A Global Routing Heuristic for FPGAs Based on Mean Field Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Sharat Prasad Power Dissipation Driven FPGA Place and Route Under Delay Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Farrahi , Majid Sarrafzadeh FPGA Technology Mapping for Power Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Jürgen Brand , Dietmar Mueller , Wolfgang Rosenstiel Specification and Synthesis of Complex Arithmetic Operators for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Miyazaki , Hiroshi Nakada , Akihiro Tsutsui , Kazuhisa Yamada , Naohisa Ohta A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] A. R. Naseer , M. Balakrishnan , Anshul Kumar An Efficient Technique for Mapping RTL Structures onto FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Volker Hamann A Testbench Design Method Suitable for FPGA-Based Prototyping of Reactive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene Goldberg , Ludmila Krasilnikova Using Consensusless Covers for Fast Operating on Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Tibor Bartos , Norbert Fristacky Formal Verification of Timing Rules in Design Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Hlawiczka , Jacek Binda Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Lichtermann , Günter Neustädter A High-Speed Rotation Processor. [Citation Graph (0, 0)][DBLP ] Conf ] P. Gramata , P. Trebaticky , Elena Gramatová The MD5 Message-Digest Algorithm in the XILINX FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Barry S. Fagin , Pichet Chintrakulchai A Reprogrammable Processor for Fractal Image Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Jebelean Implementing GCD Systolic Arrays on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Roger B. Hughes , Gerry Musgrave Formal CAD Techniques for Safety-Critical FPGA Design and Deployment in Embedded Subsystems. [Citation Graph (0, 0)][DBLP ] Conf ] T. Saluvere , D. Kerek , Hannu Tenhunen Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] R. Nguyen , P. Nguyen FPGA Based Reconfigurable Architecture for a Compact Vision System. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Rainer Kress , Helmut Reinig A New FPGA Architecture for Word-Oriented Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Athanas , A. Lynn Abbott Image Processing on a Custom Computing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Iseli , Eduardo Sanchez A Superscalar and Reconfigurable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Valentina Salapura , Michael Gschwind , Oliver Maischberger A Fast FPGA Implementation of a General Purpose Neuron. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Ast , Jürgen Becker , Reiner W. Hartenstein , Rainer Kress , Helmut Reinig , Karin Schmidt Data-Procedural Languages for FPL-based Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Daumas , Jean-Michel Muller , Jean Vuillemin Implementing On Line Arithmetic on PAM. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao-yu Chen , Xiao-ping Ling , Hideharu Amano Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Mat Newman , Wayne Luk , Ian Page Constraint-based Hierarchical Placement of Parallel Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Tormod Njølstad , Johnny Pihl , Jø Hofstad ZAREPTA: A Zero Lead-Time, All Reconfigurable System for Emulation, Prototyping and Testing of ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Richard W. Wieler , Zaifu Zhang , Robert D. McLeod Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Benner , Rolf Ernst , Ingo Könenkamp , Ulrich Holtmann , P. Schüler , H.-C. Schaub , N. Serafimov FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Brent Ward , J. D. Sterling Babcock FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping of Subsystems. [Citation Graph (0, 0)][DBLP ] Conf ] Bradly K. Fawcett , Steven H. Kelem FPGA Development Tools: Keeping Pace with Design Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Steven H. Kelem Meaningful Benchmarks for Logic Optimization of Table-Lookup FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] David Lam Educational Use of Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Bradly K. Fawcett , Nick Sawyer , Tony Williams HardWire: A Risk-Free FPGA-to-ASIC Migration Path. [Citation Graph (0, 0)][DBLP ] Conf ] Nigel Toon Reconfigurable Hardware from Programmable Logic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Attila Katona , Péter Szolgay On some Limits of XILINX Based Control Logic Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Cadek , Peter C. Thorwartl , Georg P. Westphal Experiences of Using XBLOX for Implementing a Digital Filter Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Nigel Toon Continuous Interconnect Provides Solution to Density/Performance Trade-Off in Programmable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Om P. Agrawal A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght , David McConnell , Hugh Dick Design Experience with Fine-Grained FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Leaver FPGA Routing Structures from Real Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] André Klindworth A Tool-Set for Simulating Altera-PLDs Using VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] John Ant. Hallas , Evaggelinos P. Mariatos , Michael K. Birbas , Alexios N. Birbas , Constantinos E. Goutis A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Gerd vom Bögel , Petra Nauber , Jörg Winkler A Design Environment with Emulation of Prototypes for Hardware/Software Systems Using XILINX FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jouni Isoaho , Axel Jantsch , Hannu Tenhunen DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Cowen , S. Monaghan Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic- based Custom Computing Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jirí Danecek , Alois Pluhácek , Michal Servít The Architecture of a General-Purpose Processor Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gschwind , Christian Mautner The Design of a Stack-Based Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Akil , Marcelo Alves de Barros Implementation and Performance Evaluation of an Image Pre-Processing Chain on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] E. P. Kalosha , Vyacheslav N. Yarmolik , Mark G. Karpovsky Signature Testability of PLA. [Citation Graph (0, 0)][DBLP ] Conf ] Ibrahim bin Mat , James M. Noras A FPL Prototyping Package with a C++ Interface for the PC Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Juan J. Rodríguez-Andina , J. Alvarez , Enrique Mandado Design of Safety Systems Using Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] J. C. Debize , R. J. Glaise A Job Dispatcher-Collector Made of FPGAs for a Centralized Voice server. [Citation Graph (0, 0)][DBLP ] Conf ] Jo Depreitere , Henk Neefs , Herwig Van Marck , Jan Van Campenhout , Roel Baets , Bart Dhoedt , Hugo Thienpont , Irina Veretennicoff An Optoelectronic 3-D Field Programmable Gate Array. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Sudip Nag On Channel Architecture and Routability for FPGAs Under Faulty Conditions. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Isshiki , Wayne Wei-Ming Dai Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM). [Citation Graph (0, 0)][DBLP ] Conf ] Stephan W. Gehring , Stefan H.-M. Ludwig , Niklaus Wirth A Laboratory for a Digital Design Course Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Meyer-Bäse , Anke Meyer-Bäse , W. Hilberg COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Georg J. Kempa , Peter Rieger MARC: A Macintosh NUBUS-Expansion Board Based Reconfigurable Test System for Validating Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght , Jon Stockwood , J. Law , D. Girma Artificial Neural Network Implementation on a Fine-Grained FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] 