Conferences in DBLP
Tony Stansfield , Ian Page The Design of a New FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] J. Turner , Richard Cliff , W. Leong , Cameron McClintock , Ninh Ngo , K. Nguyen , C. K. Sung , B. Wang , J. Watson Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. [Citation Graph (0, 0)][DBLP ] Conf ] Rob Payne Self-Timed FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Churcher , Tom Kean , Bill Wilkie XC6200 FastmapTM Processor Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Snider , Philip Kuekes , W. Bruce Culbertson , Richard J. Carter , Arnold S. Berger , Rick Amerson The Teramac Configurable Computer Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Miyazaki , Kazuhisa Yamada , Akihiro Tsutsui , Hiroshi Nakada , Naohisa Ohta Telecommunication-Oriented FPGA and Dedicated CAD System. [Citation Graph (0, 0)][DBLP ] Conf ] Paul A. Dunn A Configurable Logic Processor for Machine Vision. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Schulz Extending DSP-Boards with FPGA-Based Structures of Interconnection. [Citation Graph (0, 0)][DBLP ] Conf ] Ramana V. Rachakonda , Peter M. Athanas , A. Lynn Abbott High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Beaumont Using FPGAs as Control Support in MIMD Executions. [Citation Graph (0, 0)][DBLP ] Conf ] Fabio Guerrero , James M. Noras Customised Hardware Based on the REDOC III Algorithm for High-Performance Date Ciphering. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian Lawrence , Andrew Kay , Wayne Luk , Toshio Nomura , Ian Page Using Reconfigurable Hardware to Speed up Product Development and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Casselman , Michael Thornburg , John Schewel Creation of Hardware Objects in a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Laurence E. Turner , Peter J. W. Graumann Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] A. R. Naseer , M. Balakrishnan , Anshul Kumar Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo I. Boemo , Guillermo González de Rivera , Sergio López-Buedo , Juan M. Meneses Some Notes on Power Management on FPGA-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Keith R. Dimond An Automatic Technique for Realising User Interaction Processing in PLD Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Carol A. Fields The Proper Use of Hierarchy in HDL-Based High Density FPGA Design. [Citation Graph (0, 0)][DBLP ] Conf ] William P. Marnane , C. N. Jordan , F. J. O'Reilly Compiling Regular Arrays onto FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Shaori Guo , Wayne Luk Compiling Ruby into FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Greaves The CSYN Verilog Compiler and Other Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gschwind , Valentina Salapura A VHDL Design Methodology for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Maziar Khosravipour , Herbert Grünbacher VHDL-Based Rapid Hardware Prototyping Using FPGA Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Weinhardt Integer Programming for Partitioning in Software Oriented Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Kristin Ahrens Test Standard Serves Dual Role as On-Board Programming Solution. [Citation Graph (0, 0)][DBLP ] Conf ] U. Zahm , Thomas Hollstein , Hans-Jürgen Herpel , Norbert Wehn , Manfred Glesner Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Jebelean FPGA Implementation of a Rational Adder. [Citation Graph (0, 0)][DBLP ] Conf ] André Klindworth FPLD Implementation of Computation over Finite Fields GF(2m ) with Applications to Error Control Coding. [Citation Graph (0, 0)][DBLP ] Conf ] G. Panneerselvam , Peter J. W. Graumann , Laurence E. Turner Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Nabeel Shirazi , Peter M. Athanas , A. Lynn Abbott Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Russell J. Petersen , Brad L. Hutchings An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Lee An FPGA Prototype for a Multiplierless FIR Filter Built Using the Logarithmic Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Laurence E. Turner , Peter J. W. Graumann , S. G. Gibb BIT-Serial FIR Filters with CSD Coefficients for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] M. Atia , J. Bowles , D. W. Clarke , M. P. Henry , Ian Page , J. Randall , J. Yang A Self-Validating Temperature Sensor Implemented in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alan S. Wenban , Geoffrey Brown , John O'Leary Developing Interface Libraries for Reconfigurable Data Acquisition Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Jürgen Herpel , Ulrike Ober , Manfred Glesner Prototype Generation of Application-Specific Embedded Controllers for Microsystems. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Graham , Brent E. Nelson A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2. [Citation Graph (0, 0)][DBLP ] Conf ] Massimiliano Corba , Zoran Ninkov Modular Architecture for Real-Time Astronomical Image Processing with FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] D. R. Woodward , Ian Page , D. C. Levy , R. G. Harley A Programmable I/O System for Real-Time AC Drive Control Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Rajani Cuddapah , Massimiliano Corba Reconfigurable Logic for Fault-Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Guccione , Mario J. Gonzalez Supercomputing with Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale , Aaron Marks Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght , Hugh Dick , Gordon McGregor , David McConnell , Jon Stockwood Prototyping Environment for Dynamically Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Brad L. Hutchings , Michael J. Wirthlin Implementation Approaches for Reconfigurable Logic Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner , John Gray Use of Reconfigurability in Variable-Length Code Detection at Video Rates. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Guccione , Mario J. Gonzalez Classification and Performance of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] 