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Conferences in DBLP
- David Robinson, Gordon McGregor, Patrick Lysaght
New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:1-8 [Conf]
- Wayne Luk, Steve McKeever
Pebble: A Language for Parametrised and Reconfigurable Hardware Design. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:9-18 [Conf]
- Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo Oliveira, Konstantin Kondratjuk
Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:19-28 [Conf]
- Reiner W. Hartenstein, Michael Herz, Frank Gilbert
Designing for Xilinx XC6200 FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:29-38 [Conf]
- Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
Perspectives of Reconfigurable Computing in Research, Industry and Education. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:39-48 [Conf]
- Gordon J. Brebner
Field-Programmable Logic: Catalyst for New Computing Paradigms. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:49-58 [Conf]
- Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
Run-Time Management of Dynamically Recongigurable Designs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:59-68 [Conf]
- Marco Platzner, Giovanni De Micheli
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:69-78 [Conf]
- Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:79-88 [Conf]
- Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier
A Knowledge-Based System for Prototyping on FPFAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:89-98 [Conf]
- Robert Macketanz, Wolfgang Karl
JVX - A Rapid Prototyping System Based on Java and FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:99-108 [Conf]
- Joy Shetler, Brian Hemme, Chia Yang, Christopher Hinsz
Prototyping New ILP Architectures Using FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:109-118 [Conf]
- Samary Baranov
CAD System for ASM and FSM Synthesis. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:119-128 [Conf]
- John M. Emmert, Akash Randhar, Dinesh Bhatia
Fast Floorplanning for FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:129-138 [Conf]
- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:139-148 [Conf]
- Gunter Haug, Wolfgang Rosenstiel
Reconfigurable Hardware as Shared Resource in Multipurpose Computers. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:149-158 [Conf]
- Scott H. Robinson, Michael P. Chaffrey, Mark E. Dunham
Reconfigurable Computer Array: The Bridge between High Speed Sensors and Low Speed Computing. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:159-168 [Conf]
- Wayne Luk, P. Andreou, Arran Derbyshire, F. Dupont-De-Dinechin, J. Rice, Nabeel Shirazi, D. Siganos
A Reconfigurable Engine for Real-Time Video Processing. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:169-178 [Conf]
- Frank-Michael Renner, Jürgen Becker, Manfred Glesner
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:179-188 [Conf]
- Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:189-198 [Conf]
- Adam Donlin
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:199-208 [Conf]
- Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna
REACT: Reactive Environment for Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:209-217 [Conf]
- Stephen Charlwood, Philip James-Roxby
Evaluation of the XC6200-series Architecture for Cryptographic Applications. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:218-227 [Conf]
- Ali Zakerolhosseini, Peter Lee, Ed Horne
An FPFA Based Object Recognition Machine. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:228-237 [Conf]
- Georg Acher, Wolfgang Karl, Markus Leberecht
PCI-SCI Protocol Translations: Applying Microprogramming Concepts to FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:238-247 [Conf]
- Timothy J. Callahan, John Wawrzynek
Instruction-Level Parallelism for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:248-257 [Conf]
- Gordon McGregor, David Robinson, Patrick Lysaght
A Hardwar/Software Co-design Environment for Reconfigurable Logic Systems. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:258-267 [Conf]
- Kiran Bondalapati, Viktor K. Prasanna
Mapping Loops onto Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:268-277 [Conf]
- Sameh W. Asaad, Kevin Warren
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:278-287 [Conf]
- Rainer Kress, Andreas Pyttel
High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:288-297 [Conf]
- Nicholas McKay, Satnam Singh
Dynamic Specialisation of XC6200 FPGAs by Parial Evaluation. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:298-307 [Conf]
- Steve Guccione
WebScope: A Circuit Debug Tool. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:308-315 [Conf]
- Dominique Lavenier, Yannick Saouter
Computing Goldbach Partitions Using Pseudo-random Bit Generator Operators on a FPFA Systolic Array. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:316-325 [Conf]
- Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
Solving Boolean Satisfiability with Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:326-335 [Conf]
- Juri Põldre, Kalle Tammemäe, Marek Mandre
Modular Exponent Realization on FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:336-347 [Conf]
- Béla Fehér, Gábor Szedö
Cost Effective 2×2 Inner Product Processors. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:348-355 [Conf]
- Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino
A Field-Programmable Gate-Array System for Evolutionary Computation. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:356-365 [Conf]
- Toshiaki Miyazaki, Kazuhiro Shirakawa, Masaru Katayama, Takahiro Murooka, Atsushi Takahara
A Transmutable Telecom System. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:366-375 [Conf]
- Bozidar Radunovic, Veljko M. Milutinovic
A Survey of Reconfigurable Computing Architectures. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:376-385 [Conf]
- N. L. Miller, Steven F. Quigley
A Novel Field Programmable Gat Array Architecture for High Speed Arithmetic Processing. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:386-390 [Conf]
- Donald MacVicar, Satnam Singh
Accelerating DTP with Reconfigurable Computing Engines. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:391-395 [Conf]
- Carmen N. Ojeda-Guerra, Roberto Esper-Chaín, M. Estupiñán, Elsa M. Macías, Álvaro Suárez
Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and Computations. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:396-400 [Conf]
- Gordon J. Brebner
An Interactive Datasheet for the Xilinx XC6200. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:401-405 [Conf]
- Neil Woolfries, Patrick Lysaght, Stephen Marshall, Gordon McGregor, David Robinson
Fast Adaptive Image Processing in FPGAs Using Stack Filters. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:406-410 [Conf]
- Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:411-415 [Conf]
- Neil W. Bergmann, Peter R. Sutton
A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable Logic. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:416-420 [Conf]
- Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada
Maestro-Link: A High Performance Interconnect for PC Cluster. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:421-425 [Conf]
- Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Ryusuke Konishi, Norbert Imlig
A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:426-430 [Conf]
- Pedro Merino, Juan Carlos López, Margarida F. Jacome
A Hardwar Operating System for Dynamic Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:431-435 [Conf]
- Elena Cerro-Prada, Philip James-Roxby
High Speed Low Level Image Processing on FPGAs Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:436-440 [Conf]
- Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:441-445 [Conf]
- István Vassányi
Implementing Processor Arrays on FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:446-450 [Conf]
- Samuel Holmström, Kaisa Sere
Reconfigurable Hardware - A Study in Codesign. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:451-455 [Conf]
- Claude Ackad
Statechart-Based HW/SW-Codesign of a Multi-FPGA-Board and a Microprocessor. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:456-460 [Conf]
- Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx
Simulation of ATM Switches Using Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:461-465 [Conf]
- Tero Rissa, Tommi Mäkeläinen, Jarkko Niittylahti, Jouni Siirtola
Fast Prototyping Using System Emulators. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:466-470 [Conf]
- Andreas Dandalis, Viktor K. Prasanna
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:471-475 [Conf]
- Igor Lemberski, M. Ratniece
XILINX4000 Architecture-Driven Synthesis for Speed. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:476-480 [Conf]
- Valeri Tomachev
The PLD-Implementation of Boolean Function Characterized by Minimum Delay. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:481-484 [Conf]
- A. Abo Shosha, P. Reinhart, F. Rongen
Reconfigurable PCI-Bus Interface (RPCI). [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:485-489 [Conf]
- Andrej Trost, Andrej Zemva, Baldomir Zajc
Programmabel Prototyping System for Image Processing. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:490-494 [Conf]
- J. Fischer, C. Müller, H. Kurz
A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:495-499 [Conf]
- Andreas Döring, Wolfgang Obelöer, Gunther Lustig
Programming and Implementation of Reconfigurable Routers. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:500-504 [Conf]
- María José Moure, María Dolores Valdés, Enrique Mandado
Virtual Instruments Based on Reconfigurable Logic. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:505-509 [Conf]
- Christian Siemers, Dietmar P. F. Möller
The >S<puter: Introducing a Novel Concept for Dispatching Instructions Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:510-514 [Conf]
- Loïc Lagadec, Bernard Pottier
A 6200 Model and Editor Based on Object Technology. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:515-519 [Conf]
- Michael Eisenring, Jürgen Teich
Interfacing Hardware and Software. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:520-524 [Conf]
- James Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig
Generating Layouts for Self-implementing Modules. [Citation Graph (0, 0)][DBLP] FPL, 1998, pp:525-529 [Conf]
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