Conferences in DBLP
Tsugio Makimoto The Rising Wave of Field Programmability. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Govindarajan , Ranga Vemuri Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. [Citation Graph (0, 0)][DBLP ] Conf ] Johan Ditmar , Kjell Torkelsson , Axel Jantsch A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Xinan Tang , Manning Aalsma , Raymond Jou A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Marios Iliopoulos , Theodore Antonakopoulos Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hamish Fallside , Michael John Sebastian Smith Internet Connected FPL. [Citation Graph (0, 0)][DBLP ] Conf ] Frank-Michael Renner , Jürgen Becker , Manfred Glesner Field Programmable Communication Emulation and Optimization for Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Helena Krupnova , Gabriele Saucier FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Kress , Andreas Pyttel , Alexander Sedlmeier FPGA-Based Prototyping for Product Definition. [Citation Graph (0, 0)][DBLP ] Conf ] E. Cantó , Juan Manuel Moreno , Joan Cabestany , I. Lacadena , Josep Maria Insenser Implementation of Virtual Circuits by Means of the FIPSOC Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Jörn Gause , Peter Y. K. Cheung , Wayne Luk Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. [Citation Graph (0, 0)][DBLP ] Conf ] Reetinder P. S. Sidhu , Sameer Wadhwa , Alessandro Mei , Viktor K. Prasanna A Self-Reconfigurable Gate Array Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Harald Simmler , L. Levinson , Reinhard Männer Multitasking on FPGA Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Milan Vasilko Design Visualisation for Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Robinson , Patrick Lysaght Verification of Dynamically Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] T. Bartzick , M. Henze , J. Kickler , K. Woska Design of a Fault Tolerant FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Rob McCready Real-Time Face Detection on a Configurable Hardware System. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Pfeifer Multifunctional Programmable Single-Board CAN Monitoring Module. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Tomaszewicz Self-Testing of Linear Segments in User-Programmed FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] G. Lías , María Dolores Valdés , Miguel A. Domínguez , María José Moure Implementing a Fieldbus Interface Using an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Srini Krishnamoorthy , Sriram Swaminathan , Russell Tessier Area-Optimized Technology Mapping for Hybrid FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Joerg Abke , Erich Barke CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sushil Chandra Jain , Anshul Kumar , Shashi Kumar Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Helge Anderson , Jim Saunders , Sudip Nag , Chari Madabhushi , Rajeev Jayaraman A Placement Algorithm for FPGA Designs with Multiple I/O Standards. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Kropp , Carsten Reuter A Mapping Methodology for Code Trees onto LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Torresen Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiki Yamaguchi , Akira Miyashita , Tsutomu Maruyama , Tsutomu Hoshino A Co-processor System with a Virtex FPGA for Evolutionary Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Christine Bauer , Peter Zipf , Hans Wojtkowiak System Design with Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jihan Zhu , George J. Milne Implementing Kak Neural Networks on a Reconfigurable Computing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Selene Maya , Rocio Reynoso , César Torres , Miguel Arias-Estrada Compact Spiking Neural Network Implementation in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play? [Citation Graph (0, 0)][DBLP ] Conf ] John S. McCaskill , Patrick Wagler From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell A Specific Test Methodology for Symmetric SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Becker , Thilo Pionteck , Manfred Glesner DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. [Citation Graph (0, 0)][DBLP ] Conf ] A. Blaickner , O. Nagy , Herbert Grünbacher Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Revés , Antoni Gelonch , Ferran Casadevall , José L. García Software Radio Reconfigurable Hardware System (SHaRe). [Citation Graph (0, 0)][DBLP ] Conf ] Javier Ramírez , Antonio García , Pedro G. Fernández , Luis Parrilla , Antonio Lloris-Ruíz Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Scott McMillan , Steve Guccione Partial Run-Time Reconfiguration Using JRTR. [Citation Graph (0, 0)][DBLP ] Conf ] Xue-Jie Zhang , Kam-Wing Ng , Wayne Luk A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tero Rissa , Jarkko Niittylahti A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hossam A. ElGindy , Martin Middendorf , Hartmut Schmeck , Bernd Schmidt Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Michael Herz , Thomas Hoffmann , Ulrich Nageldinger Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Paul M. Heysters , Jaap Smit , Gerard J. M. Smit , Paul J. M. Havinga Mapping of DSP Algorithms on Field Programmable Function Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Stefanovic , Margaret Martonosi On Availability of Bit-Narrow Operations in General-Purpose Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Radhika S. Grover , Weijia Shang , Qiang Li A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Wolz , Reiner Kolla A New Floorplanning Method for FPGA Architectural Research. [Citation Graph (0, 0)][DBLP ] Conf ] Sameer Wadhwa , Andreas Dandalis Efficient Self-Reconfigurable Implementations Using On-chip Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Glasmacher , Kai Woska Design and Implementation of an XC6216 FPGA Model in Verilog. [Citation Graph (0, 0)][DBLP ] Conf ] Jernej Andrejas , Andrej Trost Reusable DSP Functions in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] M. Redekopp , Andreas Dandalis A Parallel Pipelined SAT Solver for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Abdellah Touhafi A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Ou Yamamoto , Yuichiro Shibata , Hitoshi Kurosawa , Hideharu Amano A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Bellis , William P. Marnane A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Melnikoff , Philip James-Roxby , Steven F. Quigley , Martin J. Russell Reconfigurable Computing for Speech Recognition: Preliminary Findings. [Citation Graph (0, 0)][DBLP ] Conf ] Hagen Ploog , Mathias Schmalisch , Dirk Timmermann Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Miomo , Koichi Yasuoka , Masanori Kanazawa The Fastest Multiplier on FPGAs with Redundant Binary Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Enzler , Tobias Jeger , Didier Cottet , Gerhard Tröster High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Russell Tessier , Heather Giza Balancing Logic Utilization and Area Efficiency in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Emmert , Charles E. Stroud , Jason A. Cheatham , Andrew M. Taylor , Pankaj Kataria , Miron Abramovici Performance Penalty for Fault Tolerance in Roving STARs. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Qiao , Makoto Ikeda , Kunihiro Asada Optimum Functional Decomposition for LUT-Based FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Eisenring , Marco Platzner Optimization of Run-Time Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Kean It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Yuichiro Shibata , Masaki Uno Reconfigurable Systems: New Activities in Asia. [Citation Graph (0, 0)][DBLP ] Conf ] Oskar Mencer , Heiko Hübert , Martin Morf , Michael J. Flynn StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. [Citation Graph (0, 0)][DBLP ] Conf ] Eylon Caspi , Michael Chu , Randy Huang , Joseph Yeh , John Wawrzynek , André DeHon Stream Computations Organized for Reconfigurable Execution (SCORE). [Citation Graph (0, 0)][DBLP ] Conf ] Holger Lange , Andreas Koch Memory Access Schemes for Configurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Döring , Gunther Lustig Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Arran Derbyshire , Wayne Luk Combining Serialisation and Reconfiguration for FPGA Designs. [Citation Graph (0, 0)][DBLP ] Conf ] George A. Constantinides , Peter Y. K. Cheung , Wayne Luk Multiple-Wordlength Resource Binding. [Citation Graph (0, 0)][DBLP ] Conf ] Milan Vasilko , Graham Benyon-Tinker Automatic Temporal Floorplanning with Guaranteed Solution Feasibility. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Aoyama , Hiroshi Sawada , Akira Nagoya , Kazuo Nakajima A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Takayama , Yuichiro Shibata , Keisuke Iwai , Hideharu Amano Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Bernardo Kastrup , Jeroen Trum , Orlando Moreira , Jan Hoogerbrugge , Jef L. van Meerbergen Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Diessel , George J. Milne Behavioural Language Compilation with Virtual Hardware Management. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Skylarov Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Shuichi Ichikawa , Hidemitsu Saito , Lerdtanaseangtham Udorn , Kouji Konishi Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Martyn Edwards , Peter Green The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Courtney , Richard H. Turner , Roger Woods Multiplexer Based Reconfiguration for Virtex Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Bobda , Thomas Lehmann Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Siemers Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Winnie W. Cheng , Steven J. E. Wilton , Babak Hamidzadeh FPGA Implementation of a Prototype WDM On-Line Scheduler. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Hildebrandt , Dirk Timmermann An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sergej Sawitzki , Jens Schönherr , Rainer G. Spallek , Bernd Straube Formal Verification of a Reconfigurable Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Gadea Gironés , Vicente Herrero , Angel Sebastia , Antonio Mocholí Salcedo The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Lecurieux Lafayette Programmable System Level Integration Brings System-on-Chip Design to the Desktop. [Citation Graph (0, 0)][DBLP ] Conf ] A. Hilton , J. Hall On Applying Software Development Best Practice to FPFAs in Safety Critical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Brandon Blodget Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyoshi Kobori , Tsutomu Maruyama , Tsutomu Hoshino High Speed Computation of Lattice gas Automata with FPFA. [Citation Graph (0, 0)][DBLP ] Conf ] Tsunemichi Shiozawa , Norbert Imlig , Kouichi Nagami , Kiyoshi Oguri , Akira Nagoya , Hiroshi Nakada An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan Matasaru , Tudor Jebelean FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. [Citation Graph (0, 0)][DBLP ] Conf ] Lukás Sekanina , Azeddien M. Sllame Toward Uniform Approach to Design of Evolvable Hardware Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andrej Trost , Andrej Zemva , Baldomir Zajc Educational Programmable Hardware Prototyping and Verification System. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Hoffmann , Bernd Ulmann , Klaus-Peter Völkmann , Stefan Waldschmidt A Stream Processor Architecture Based on the Configurable CEPRA-S. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Hatnik , Jürgen Haufe , Peter Schwarz An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Kalle Tammemäe , T. Evartson FPL Curriculum at Tallinn Technical University. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Michel Raczinski , Stéphane Sladek The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] André Brinkmann , Dominik Langen , Ulrich Rückert A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Juanjo Noguera , Rosa M. Badia Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Phillips Wireless Base Station Design Using a Reconfigurable Communications Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Erwan Fabiani , Dominique Lavenier Placement of Linear Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] 