Conferences in DBLP
Paul Master The Age of Adaptive Computing Is Here. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein Disruptive Trends by Data-Stream-Based Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner Multithreading for Logic-Centric Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Siavash Bayat Sarmadi , Seyed Ghassem Miremadi , Ghazanfar Asadi , Ali Reza Ejlali Fast Prototyping with Co-operation of Simulation and Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] Helena Krupnova , Veronique Meurou , Christophe Barnichon , Carlos Serra , Farid Morsi How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. [Citation Graph (0, 0)][DBLP ] Conf ] Quoc Thai Ho , Jean-Baptiste Rigaud , Laurent Fesquet , Marc Renaudin , Robin Rolland Implementing Asynchronous Circuits on LUT Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Beniamino Di Martino , Nicola Mazzocca , Giacinto Paolo Saggese , Antonio G. M. Strollo A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Compton , Akshay Sharma , Shawn Phillips , Scott Hauck Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. [Citation Graph (0, 0)][DBLP ] Conf ] Jawad Khan , Manish Handa , Ranga Vemuri iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Sima , Stamatis Vassiliadis , Sorin Cotofana , Jos T. J. van Eijndhoven , Kees A. Vissers Field-Programmable Custom Computing Machines - A Taxonomy -. [Citation Graph (0, 0)][DBLP ] Conf ] Katarzyna Leijten-Nowak , Jef L. van Meerbergen Embedded Reconfigurable Logic Core for DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Cardells-Tormo , Javier Valls-Coquillat , Vicenc Almenar-Terre , Vicente Torres-Carot Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Dick , Fred Harris FPGA QAM Demodulator Design. [Citation Graph (0, 0)][DBLP ] Conf ] Guy G. Lemieux , David M. Lewis Analytical Framework for Switch Block Design. [Citation Graph (0, 0)][DBLP ] Conf ] Aneesh Koorapaty , Lawrence T. Pileggi Modular, Fabric-Specific Synthesis for Programmable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbing Fan , Jiping Liu , Yu-Liang Wu , Chak-Chung Cheung On Optimum Designs of Universal Switch Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Robertson , James Irvine , Patrick Lysaght , David Robinson Improved Functional Simulation of Dynamically Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio López-Buedo , Paula Riviere , Pablo Pernas , Eduardo I. Boemo Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard J. M. Smit , Paul J. M. Havinga , Lodewijk T. Smit , Paul M. Heysters , Michèl A. J. Rosien Dynamic Reconfiguration in Mobile Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Edson L. Horta , John W. Lockwood , Sergio Takeo Kofuji Using PARBIT to Implement Partial Run-Time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Turner , Roger Woods , Tim Courtney Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Melnikoff , Steven F. Quigley , Martin J. Russell Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models. [Citation Graph (0, 0)][DBLP ] Conf ] Antony Jamin , Petri Mähönen FPGA Implementation of the Wavelet Packet Transform for High Speed Communications. [Citation Graph (0, 0)][DBLP ] Conf ] A. Carreira , T. W. Fox , L. E. Turner A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM . [Citation Graph (0, 0)][DBLP ] Conf ] Valavan Manohararajah , Terry Borer , Stephen Dean Brown , Zvonko G. Vranesic Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] PariVallal Kannan , Shankar Balachandran , Dinesh Bhatia Rapid and Reliable Routability Estimation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Danek , Zdenek Muzikár Integrated Iterative Approach to FPGA Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Lucídio A. F. Cabral , Júlio S. Aude , Nelson Maculan TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rafal Kielbik , Juan Manuel Moreno , Andrzej Napieralski , Grzegorz Jablonski , Tomasz Szymanski High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiki Yamaguchi , Yosuke Miyajima , Tsutomu Maruyama , Akihiko Konagaya High Speed Homology Search Using Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Dyer , Christian Plessl , Marco Platzner Partially Reconfigurable Cores for Xilinx Virtex. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel G. Gericota , Gustavo R. Alves , Miguel L. Silva , José M. M. Ferreira On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kara K. W. Poon , Andy Yan , Steven J. E. Wilton A Flexible Power Model for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Oswaldo Cadenas , Graham M. Megson A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Martina , Guido Masera , Gianluca Piccinini , Fabrizio Vacca , Maurizio Zamboni Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Elias Todorovich , M. Gilabert , Gustavo Sutter , Sergio López-Buedo , Eduardo I. Boemo A Tool for Activity Estimation in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Sutter , Elias Todorovich , Sergio López-Buedo , Eduardo I. Boemo FSM Decomposition for Low Power in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled Benkrid , Danny Crookes , Abdsamad Benkrid , S. Belkacemi A Prolog-Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Hok Ho , Philip Heng Wai Leong , Kuen Hung Tsoi , Ralf Ludewig , Peter Zipf , Alberto García Ortiz , Manfred Glesner Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Ivo Bolsens Challenges and Opportunities for FPGA Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Kirimura , Yoshifumi Takamoto , Takanori Mori , Keiichi Yasumoto , Akio Nakata , Teruo Higashino Design and Implementation of FPGA Circuits for High Speed Network Monitors. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale , Dave Dubois , Andy Dubois , Mike Boorman , Steve Poole , Vic Hogsett Granidt: Towards Gigabit Rate Network Intrusion Detection Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Channakeshav , Kuan Zhou , Jong-Ru Guo , Chao You , Bryan S. Goda , Russell P. Kraft , John F. McDonald Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Tyson S. Hall , Paul E. Hasler , David V. Anderson Field-Programmable Analog Arrays: A Floating-Gate Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Tanigawa , Tetsuo Hironaka , Akira Kojima , Noriyoshi Yoshida A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. [Citation Graph (0, 0)][DBLP ] Conf ] Thilo Pionteck , Peter Zipf , Lukusa D. Kabulepa , Manfred Glesner A Framework for Teaching (Re)Configurable Architectures in Student Projects. [Citation Graph (0, 0)][DBLP ] Conf ] Young H. Cho , Shiva Navab , William H. Mangione-Smith Specialized Hardware for Deep Network Packet Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Buerner Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Ramírez , Antonio García U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Simon D. Haynes , Henry G. Epsom , Richard J. Cooper , Paul L. McAlpine UltraSONIC: A Reconfigurable Architecture for Video Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor W. Fox , Laurence E. Turner Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Staller , Peter Dillinger , Reinhard Männer Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Luc Beuchat , Arnaud Tisserand Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Altaf Abdul Gaffar , Wayne Luk , Peter Y. K. Cheung , Nabeel Shirazi , James Hwang Automating Customisation of Floating-Point Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ju-wook Jang , Seonil Choi , Viktor K. Prasanna Energy-Efficient Matrix Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Shay Ping Seng , Wayne Luk , Peter Y. K. Cheung Run-Time Adaptive Flexible Instruction Processors. [Citation Graph (0, 0)][DBLP ] Conf ] José T. de Sousa , Fernando M. Gonçalves , Nuno Barreiro , João Moura DARP - A Digital Audio Reconfigurable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Charlwood , Jonathan Mangnall , Steven F. Quigley System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt K. Ting , Steve C. L. Yuen , Kin-Hong Lee , Philip Heng Wai Leong An FPGA Based SHA-256 Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zipf , Manfred Glesner , Christine Bauer , Hans Wojtkowiak Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rudolf Matousek , Milan Tichý , Zdenek Pohl , Jiri Kadlec , Chris Softley , Nick Coleman Logarithmic Number System and Floating-Point Arithmetics on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Roesler , Brent E. Nelson Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Silviu M. S. A. Chiricescu , Michael A. Schuette , Robin Glinton , Herman Schmit Morphable Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Pavle Belanovic , Miriam Leeser A Library of Parameterized Floating-Point Modules and Their Use. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Stansfield Wordlength as an Architectural Parameter for Reconfigurable Computing Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Baleani , Massimo Conti , Alberto Ferrari , Valerio Frascolla , Alberto L. Sangiovanni-Vincentelli An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Grant B. Wigley , David A. Kearney , David Warren Introducing ReConfigME: An Operating System for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Reetinder P. S. Sidhu , Viktor K. Prasanna Efficient Metacomputation Using Self-Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Arias-Estrada , Eduardo Rodríguez-Palacios An FPGA Co-processor for Real-Time Visual Tracking. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor Fischer , Milos Drutarovský , Rastislav Lukac Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Abbes Amira , Ahmed Bouridane , Peter Milligan , Faycal Bensaali Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Nazeeh Aranki , Alexander Moopenn , Raoul Tawel Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Kerins , Emanuel M. Popovici , William P. Marnane , Patrick Fitzpatrick Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). [Citation Graph (0, 0)][DBLP ] Conf ] Antti Hämäläinen , Matti Tommiska , Jorma Skyttä 8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanuel A. Moreira , Paul L. McAlpine , Simon D. Haynes Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Jacques Quisquater , François-Xavier Standaert , Gaël Rouvroy , Jean-Pierre David , Jean-Didier Legat A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Rudy Lauwereins Creating a World of Smart Re-configurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Théodore Marescaux , Andrei Bartic , Diederik Verkest , Serge Vernalde , Rudy Lauwereins Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Wesley J. Landaker , Michael J. Wirthlin , Brad L. Hutchings Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP ] Conf ] Tuomas Valtonen , Jouni Isoaho , Hannu Tenhunen The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Zbigniew Kokosinski , Wojciech Sikora An FPGA Implementation of a Multi-comparand Multi-search Associative Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Labbé , Annie Pérez AES Implementation on FPGA: Time - Flexibility Tradeoff. [Citation Graph (0, 0)][DBLP ] Conf ] François Koeune , Gaël Rouvroy , François-Xavier Standaert , Jean-Jacques Quisquater , Jean-Pierre David , Jean-Didier Legat An FPGA Implementation of the Linear Cryptanalysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Budiu , Seth Copen Goldstein Compiling Application-Specific Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] João M. P. Cardoso , Markus Weinhardt XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Justin L. Tripp , Preston A. Jackson , Brad L. Hutchings Sea Cucumber: A Synthesizing Compiler for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Carletta , M. D. Rayman Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Meyer-Bäse , Javier Ramírez , Antonio García Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Cardells-Tormo , Javier Valls-Coquillat High Performance Quadrature Digital Mixers for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Oskar Mencer , Zhining Huang , Lorenz Huelsbergen HAGAR: Efficient Multi-context Graph Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Carrión Schäfer , Steven F. Quigley , Andrew H. C. Chan Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Pui Lam , Sui-Tung Mak On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Zoran A. Salcic , Partha S. Roop , Morteza Biglari-Abhari , Abbas Bigdeli REFLIX: A Processor Core for Reactive Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Venkataramani , Suraj Sudhir , Mihai Budiu , Seth Copen Goldstein Factors Influencing the Performance of a CPU-RFU Hybrid Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Sanz , José I. García-Nicolás , Isidoro Urriza Implementing Converters in FPLD. [Citation Graph (0, 0)][DBLP ] Conf ] Domingo Benitez A Quantitative Understanding of the Performance of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Buchenrieder , Ulrich Nageldinger , Andreas Pyttel , Alexander Sedlmeier Integration of Reconfigurable Hardware into System-Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Wolz , Reiner Kolla A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswamy Ramaswamy , Russell Tessier The Integration of SystemC and Hardware-Assisted Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Kaviani Using Design Hierarchy to Improve Quality of Results in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] G. Koutroumpezis , Konstantinos Tatas , Dimitrios Soudris , Spyros Blionas , Kostas Masselos , Adonios Thanailakis Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Naoto Kaneko , Hideharu Amano A General Hardware Design Model for Multicontext FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Porrmann , Ulf Witkowski , Heiko Kalte , Ulrich Rückert Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Raphaël David , Daniel Chillet , Sébastien Pillement , Olivier Sentieys A Compilation Framework for a Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Shuichi Ichikawa , Shoji Yamamoto Data Dependent Circuit for Subgraph Isomorphism Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Schmidt , Martin Novotný , Martin Jäger , Milos Becvár , Michal Jáchim Exploration of Design Space in ECDSA. [Citation Graph (0, 0)][DBLP ] Conf ] Issam Damaj , Sohaib Majzoub , Hassan B. Diab 2D and 3D Computer Graphics Algorithms under MORPHOSYS. [Citation Graph (0, 0)][DBLP ] Conf ] Spyros Blionas , Kostas Masselos , Chrissavgi Dre , Christos Drosos , F. Z. Ieromnimon , T. Pagonis , A. Pneymatikakis , Anna Tatsaki , T. Trimis , A. Vontzalidis , Dimitris Metafas A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Stephanie McBader , Luca Clementel , Alvise Sartori , Andrea Boni , Peter Lee SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Yokota , Masamichi Nagafuchi , Yoshito Mekada , Tsutomu Yoshinaga , Kanemitsu Ootsu , Takanobu Baba Real-Time Medical Diagnosis on a Multiple FPGA-based System. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuo Aoyama , Hiroshi Sawada Threshold Element-Based Symmetric Function Generators and Their Functional Extension. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Schlecker , Achim Engelhart , Werner G. Teich , Hans-Jörg Pfleiderer Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] James Hwang , Jonathan Ballagh Building Custom FIR Filters Using System Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Feske , Georg Heinrich , Berndt Fritzsche , Mark Langer SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ernest Jamro , Kazimierz Wiatr Dynamic Constant Coefficient Convolvers Implemented in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Urs Kanus , Gregor Wetekam , Johannes Hirche , Michael Meißner VIZARD II: An FPGA-based Interactive Volume Rendering System. [Citation Graph (0, 0)][DBLP ] Conf ] Naoyuki Izu , Tomonori Yokoyama , Junichiro Tsuchiya , Konosuke Watanabe , Hideharu Amano RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Filip Miletic , Rene van Leuken , Alexander de Graaf General Purpose Prototyping Platform for Data-Processor Research and Development. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyoshi Kobori , Tsutomu Maruyama High Speed Computation of Three Dimensional Cellular Automata with FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Sylvain Poussier , Hassan Rabah , Serge Weber SOPC-based Embedded Smart Strain Gage Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Yajun Ha , Radovan Hipik , Serge Vernalde , Diederik Verkest , Marc Engels , Rudy Lauwereins , Hugo De Man Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Gaudino , Vito De Feo , Marcello Chiaberge , Claudio Sansoè An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network. [Citation Graph (0, 0)][DBLP ] Conf ] Francis Calmon , M. Fathallah , P. J. Viverge , Christian Gontrand , Jordi Carrabina , P. Foussier FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Wim J. C. Melis , Peter Y. K. Cheung , Wayne Luk Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Dylan Carline , Paul Coulton A Novel Watermarking Technique for LUT Based FPGA Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Henz , Edgar Tan , Roland H. C. Yap Implementing CSAT Local Search on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Adronis Niyonkuru , Göran Eggers , Hans Christoph Zeidler A Reconfigurable Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Friebe , Steffen Köhler , Rainer G. Spallek , Henrik Juhr , Klaus Künanz A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Guccione , Eric Keller Gene Matching Using JBits. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel G. Saab , Fatih Kocan , Jacob A. Abraham Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Miyashita , Toshihito Fujiwara , Tsutomu Maruyama A Placement/Routing Approach for FPGA Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] 