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Conferences in DBLP

Field-Programmable Logic and Applications (FPL) (fpl)
2002 (conf/fpl/2002)

  1. Paul Master
    The Age of Adaptive Computing Is Here. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1-3 [Conf]
  2. Reiner W. Hartenstein
    Disruptive Trends by Data-Stream-Based Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:4- [Conf]
  3. Gordon J. Brebner
    Multithreading for Logic-Centric Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:5-14 [Conf]
  4. Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali
    Fast Prototyping with Co-operation of Simulation and Emulation. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:15-25 [Conf]
  5. Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi
    How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:26-35 [Conf]
  6. Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
    Implementing Asynchronous Circuits on LUT Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:36-46 [Conf]
  7. Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo
    A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:47-58 [Conf]
  8. Katherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck
    Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:59-68 [Conf]
  9. Jawad Khan, Manish Handa, Ranga Vemuri
    iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:69-78 [Conf]
  10. Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
    Field-Programmable Custom Computing Machines - A Taxonomy -. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:79-88 [Conf]
  11. Katarzyna Leijten-Nowak, Jef L. van Meerbergen
    Embedded Reconfigurable Logic Core for DSP Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:89-101 [Conf]
  12. Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-Carot
    Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:102-111 [Conf]
  13. Chris Dick, Fred Harris
    FPGA QAM Demodulator Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:112-121 [Conf]
  14. Guy G. Lemieux, David M. Lewis
    Analytical Framework for Switch Block Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:122-131 [Conf]
  15. Aneesh Koorapaty, Lawrence T. Pileggi
    Modular, Fabric-Specific Synthesis for Programmable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:132-141 [Conf]
  16. Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
    On Optimum Designs of Universal Switch Blocks. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:142-151 [Conf]
  17. Ian Robertson, James Irvine, Patrick Lysaght, David Robinson
    Improved Functional Simulation of Dynamically Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:152-161 [Conf]
  18. Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo
    Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:162-170 [Conf]
  19. Gerard J. M. Smit, Paul J. M. Havinga, Lodewijk T. Smit, Paul M. Heysters, Michèl A. J. Rosien
    Dynamic Reconfiguration in Mobile Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:171-181 [Conf]
  20. Edson L. Horta, John W. Lockwood, Sergio Takeo Kofuji
    Using PARBIT to Implement Partial Run-Time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:182-191 [Conf]
  21. Richard H. Turner, Roger Woods, Tim Courtney
    Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:192-201 [Conf]
  22. Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell
    Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:202-211 [Conf]
  23. Antony Jamin, Petri Mähönen
    FPGA Implementation of the Wavelet Packet Transform for High Speed Communications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:212-221 [Conf]
  24. A. Carreira, T. W. Fox, L. E. Turner
    A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:222-231 [Conf]
  25. Valavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic
    Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:232-241 [Conf]
  26. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
    Rapid and Reliable Routability Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:242-252 [Conf]
  27. Martin Danek, Zdenek Muzikár
    Integrated Iterative Approach to FPGA Placement. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:253-262 [Conf]
  28. Lucídio A. F. Cabral, Júlio S. Aude, Nelson Maculan
    TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:263-270 [Conf]
  29. Rafal Kielbik, Juan Manuel Moreno, Andrzej Napieralski, Grzegorz Jablonski, Tomasz Szymanski
    High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:271-280 [Conf]
  30. Yoshiki Yamaguchi, Yosuke Miyajima, Tsutomu Maruyama, Akihiko Konagaya
    High Speed Homology Search Using Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:281-291 [Conf]
  31. Matthias Dyer, Christian Plessl, Marco Platzner
    Partially Reconfigurable Cores for Xilinx Virtex. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:292-301 [Conf]
  32. Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. M. Ferreira
    On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:302-311 [Conf]
  33. Kara K. W. Poon, Andy Yan, Steven J. E. Wilton
    A Flexible Power Model for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:312-321 [Conf]
  34. Oswaldo Cadenas, Graham M. Megson
    A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:322-331 [Conf]
  35. Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
    Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:332-339 [Conf]
  36. Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo
    A Tool for Activity Estimation in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:340-349 [Conf]
  37. Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
    FSM Decomposition for Low Power in FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:350-359 [Conf]
  38. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:360-369 [Conf]
  39. Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, S. Belkacemi
    A Prolog-Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:370-380 [Conf]
  40. Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
    Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:381-390 [Conf]
  41. Ivo Bolsens
    Challenges and Opportunities for FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:391-392 [Conf]
  42. Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
    Design and Implementation of FPGA Circuits for High Speed Network Monitors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:393-403 [Conf]
  43. Maya Gokhale, Dave Dubois, Andy Dubois, Mike Boorman, Steve Poole, Vic Hogsett
    Granidt: Towards Gigabit Rate Network Intrusion Detection Technology. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:404-413 [Conf]
  44. Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:414-423 [Conf]
  45. Tyson S. Hall, Paul E. Hasler, David V. Anderson
    Field-Programmable Analog Arrays: A Floating-Gate Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:424-433 [Conf]
  46. Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida
    A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:434-443 [Conf]
  47. Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
    A Framework for Teaching (Re)Configurable Architectures in Student Projects. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:444-451 [Conf]
  48. Young H. Cho, Shiva Navab, William H. Mangione-Smith
    Specialized Hardware for Deep Network Packet Filtering. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:452-461 [Conf]
  49. Thomas Buerner
    Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:462-471 [Conf]
  50. Javier Ramírez, Antonio García
    U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:472-481 [Conf]
  51. Simon D. Haynes, Henry G. Epsom, Richard J. Cooper, Paul L. McAlpine
    UltraSONIC: A Reconfigurable Architecture for Video Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:482-491 [Conf]
  52. Trevor W. Fox, Laurence E. Turner
    Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:492-502 [Conf]
  53. Alexander Staller, Peter Dillinger, Reinhard Männer
    Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:503-512 [Conf]
  54. Jean-Luc Beuchat, Arnaud Tisserand
    Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:513-522 [Conf]
  55. Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang
    Automating Customisation of Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:523-533 [Conf]
  56. Ju-wook Jang, Seonil Choi, Viktor K. Prasanna
    Energy-Efficient Matrix Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:534-544 [Conf]
  57. Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
    Run-Time Adaptive Flexible Instruction Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:545-555 [Conf]
  58. José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura
    DARP - A Digital Audio Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:556-566 [Conf]
  59. Stephen Charlwood, Jonathan Mangnall, Steven F. Quigley
    System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:567-576 [Conf]
  60. Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai Leong
    An FPGA Based SHA-256 Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:577-585 [Conf]
  61. Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak
    Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:586-595 [Conf]
  62. Andrzej Krasniewski
    On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:596-606 [Conf]
  63. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:607-615 [Conf]
  64. Andrzej Krasniewski
    Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:616-626 [Conf]
  65. Rudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Chris Softley, Nick Coleman
    Logarithmic Number System and Floating-Point Arithmetics on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:627-636 [Conf]
  66. Eric Roesler, Brent E. Nelson
    Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:637-646 [Conf]
  67. Silviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman Schmit
    Morphable Multipliers. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:647-656 [Conf]
  68. Pavle Belanovic, Miriam Leeser
    A Library of Parameterized Floating-Point Modules and Their Use. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:657-666 [Conf]
  69. Tony Stansfield
    Wordlength as an Architectural Parameter for Reconfigurable Computing Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:667-676 [Conf]
  70. Massimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-Vincentelli
    An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:677-686 [Conf]
  71. Grant B. Wigley, David A. Kearney, David Warren
    Introducing ReConfigME: An Operating System for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:687-697 [Conf]
  72. Reetinder P. S. Sidhu, Viktor K. Prasanna
    Efficient Metacomputation Using Self-Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:698-709 [Conf]
  73. Miguel Arias-Estrada, Eduardo Rodríguez-Palacios
    An FPGA Co-processor for Real-Time Visual Tracking. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:710-719 [Conf]
  74. Viktor Fischer, Milos Drutarovský, Rastislav Lukac
    Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:720-729 [Conf]
  75. Abbes Amira, Ahmed Bouridane, Peter Milligan, Faycal Bensaali
    Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:730-739 [Conf]
  76. Nazeeh Aranki, Alexander Moopenn, Raoul Tawel
    Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:740-749 [Conf]
  77. Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick
    Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:750-759 [Conf]
  78. Antti Hämäläinen, Matti Tommiska, Jorma Skyttä
    8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:760-769 [Conf]
  79. Emmanuel A. Moreira, Paul L. McAlpine, Simon D. Haynes
    Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:770-779 [Conf]
  80. Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat
    A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:780-789 [Conf]
  81. Rudy Lauwereins
    Creating a World of Smart Re-configurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:790-794 [Conf]
  82. Théodore Marescaux, Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:795-805 [Conf]
  83. Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings
    Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:806-815 [Conf]
  84. Tuomas Valtonen, Jouni Isoaho, Hannu Tenhunen
    The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:816-825 [Conf]
  85. Zbigniew Kokosinski, Wojciech Sikora
    An FPGA Implementation of a Multi-comparand Multi-search Associative Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:826-835 [Conf]
  86. Anna Labbé, Annie Pérez
    AES Implementation on FPGA: Time - Flexibility Tradeoff. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:836-844 [Conf]
  87. François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat
    An FPGA Implementation of the Linear Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:845-852 [Conf]
  88. Mihai Budiu, Seth Copen Goldstein
    Compiling Application-Specific Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:853-863 [Conf]
  89. João M. P. Cardoso, Markus Weinhardt
    XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:864-874 [Conf]
  90. Justin L. Tripp, Preston A. Jackson, Brad L. Hutchings
    Sea Cucumber: A Synthesizing Compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:875-885 [Conf]
  91. Joan Carletta, M. D. Rayman
    Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:886-896 [Conf]
  92. Uwe Meyer-Bäse, Javier Ramírez, Antonio García
    Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:897-904 [Conf]
  93. Francisco Cardells-Tormo, Javier Valls-Coquillat
    High Performance Quadrature Digital Mixers for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:905-914 [Conf]
  94. Oskar Mencer, Zhining Huang, Lorenz Huelsbergen
    HAGAR: Efficient Multi-context Graph Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:915-924 [Conf]
  95. Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan
    Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:925-934 [Conf]
  96. Kai-Pui Lam, Sui-Tung Mak
    On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:935-944 [Conf]
  97. Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli
    REFLIX: A Processor Core for Reactive Embedded Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:945-945 [Conf]
  98. Girish Venkataramani, Suraj Sudhir, Mihai Budiu, Seth Copen Goldstein
    Factors Influencing the Performance of a CPU-RFU Hybrid Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:955-965 [Conf]
  99. Alfredo Sanz, José I. García-Nicolás, Isidoro Urriza
    Implementing Converters in FPLD. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:966-975 [Conf]
  100. Domingo Benitez
    A Quantitative Understanding of the Performance of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:976-986 [Conf]
  101. Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier
    Integration of Reconfigurable Hardware into System-Level Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:987-996 [Conf]
  102. Frank Wolz, Reiner Kolla
    A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:997-1006 [Conf]
  103. Ramaswamy Ramaswamy, Russell Tessier
    The Integration of SystemC and Hardware-Assisted Verification. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1007-1016 [Conf]
  104. Alireza Kaviani
    Using Design Hierarchy to Improve Quality of Results in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1017-1026 [Conf]
  105. G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis
    Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1027-1036 [Conf]
  106. Naoto Kaneko, Hideharu Amano
    A General Hardware Design Model for Multicontext FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1037-1047 [Conf]
  107. Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert
    Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1048-1057 [Conf]
  108. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    A Compilation Framework for a Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1058-1067 [Conf]
  109. Shuichi Ichikawa, Shoji Yamamoto
    Data Dependent Circuit for Subgraph Isomorphism Problem. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1068-1071 [Conf]
  110. Jan Schmidt, Martin Novotný, Martin Jäger, Milos Becvár, Michal Jáchim
    Exploration of Design Space in ECDSA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1072-1075 [Conf]
  111. Issam Damaj, Sohaib Majzoub, Hassan B. Diab
    2D and 3D Computer Graphics Algorithms under MORPHOSYS. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1076-1079 [Conf]
  112. Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, A. Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas
    A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1080-1083 [Conf]
  113. Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee
    SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1084-1087 [Conf]
  114. Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
    Real-Time Medical Diagnosis on a Multiple FPGA-based System. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1088-1091 [Conf]
  115. Kazuo Aoyama, Hiroshi Sawada
    Threshold Element-Based Symmetric Function Generators and Their Functional Extension. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1092-1096 [Conf]
  116. Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer
    Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1097-1100 [Conf]
  117. James Hwang, Jonathan Ballagh
    Building Custom FIR Filters Using System Generator. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1101-1104 [Conf]
  118. Klaus Feske, Georg Heinrich, Berndt Fritzsche, Mark Langer
    SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1105-1109 [Conf]
  119. Ernest Jamro, Kazimierz Wiatr
    Dynamic Constant Coefficient Convolvers Implemented in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1110-1113 [Conf]
  120. Urs Kanus, Gregor Wetekam, Johannes Hirche, Michael Meißner
    VIZARD II: An FPGA-based Interactive Volume Rendering System. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1114-1117 [Conf]
  121. Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano
    RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1118-1121 [Conf]
  122. Filip Miletic, Rene van Leuken, Alexander de Graaf
    General Purpose Prototyping Platform for Data-Processor Research and Development. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1122-1125 [Conf]
  123. Tomoyoshi Kobori, Tsutomu Maruyama
    High Speed Computation of Three Dimensional Cellular Automata with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1126-1130 [Conf]
  124. Sylvain Poussier, Hassan Rabah, Serge Weber
    SOPC-based Embedded Smart Strain Gage Sensor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1131-1134 [Conf]
  125. Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man
    Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1135-1138 [Conf]
  126. Roberto Gaudino, Vito De Feo, Marcello Chiaberge, Claudio Sansoè
    An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1139-1143 [Conf]
  127. Francis Calmon, M. Fathallah, P. J. Viverge, Christian Gontrand, Jordi Carrabina, P. Foussier
    FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1144-1147 [Conf]
  128. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1148-1151 [Conf]
  129. Dylan Carline, Paul Coulton
    A Novel Watermarking Technique for LUT Based FPGA Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1152-1155 [Conf]
  130. Martin Henz, Edgar Tan, Roland H. C. Yap
    Implementing CSAT Local Search on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1156-1159 [Conf]
  131. Adronis Niyonkuru, Göran Eggers, Hans Christoph Zeidler
    A Reconfigurable Processor Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1160-1163 [Conf]
  132. Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz
    A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1164-1167 [Conf]
  133. Steve Guccione, Eric Keller
    Gene Matching Using JBits. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1168-1171 [Conf]
  134. Daniel G. Saab, Fatih Kocan, Jacob A. Abraham
    Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1172-1176 [Conf]
  135. Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama
    A Placement/Routing Approach for FPGA Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1177-1182 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002