Conferences in DBLP
Mark Sullivan , Ram Chillarege Software Defects and their Impact on System Availability: A Study of Field Failures in Operating Systems. [Citation Graph (2, 0)][DBLP ] Conf ] Inhwan Lee , Ravishankar K. Iyer , Dong Tang Error/Failure Analysis Using Event Logs from Fault Tolerant Systems. [Citation Graph (0, 0)][DBLP ] Conf ] T. R. Dilenno , D. A. Yaskin , James H. Barton Fault-Tolerance Testing in the Advanced Automation System. [Citation Graph (0, 0)][DBLP ] Conf ] T. Takano , T. Yamada , K. Shutoh , Nobuyasu Kanekawa Fault Tolerance Experiments of the "Hiten" Onboard Space Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Stanion , Debashis Bhattacharya TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jaushin Lee , Janak H. Patel An Architectural Level Test Generator for a Hierarchical Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel C. Lee , Daniel P. Siewiorek Functional Test Generation for Pipelined Computer Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Doug Jewett Integrity S2: A Fault-Tolerant Unix Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Banâtre , Gilles Muller , Bruno Rochat , P. Sanchez Design Decisions for the FTM : A General Purpose Fault Tolerant Machine. [Citation Graph (0, 0)][DBLP ] Conf ] S. Webber , J. Beirne The Stratus Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] R. Raina , Peter N. Marinos Signature Analysis with Modified Linear Feedback Shift Registers (M-LFSRs). [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele , Hans-Joachim Wunderlich Signature Analysis and Test Scheduling for Self-Testable Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nirmal R. Saxena , Piero Franco , Edward J. McCluskey Bounds on Signature Analysis Aliasing for Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ram Chillarege , Robert W. Horst , Daniel P. Siewiorek , R. S. Swarz Challenges in Designing Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP ] Conf ] T. Bissett Designing Error Detection and Recovery for a Fault-Tolerant Computer System. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lenoski Practical Problems in the Design of Fault-Tolerant Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Jack Isenberg Evolving Systems for Continuous Availability. [Citation Graph (0, 0)][DBLP ] Conf ] J. J. Stiffler On Establishing Fault Tolerance Objectives. [Citation Graph (0, 0)][DBLP ] Conf ] D. Steinfeld Design Process for High-Availability Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dechang Gu , Daniel J. Rosenkrantz , S. S. Ravi Construction and Analysis of Fault-Secure Multiprocessor Schedules. [Citation Graph (0, 0)][DBLP ] Conf ] M. Tsunoyama , S. Naito A Fault-Tolerant FFT Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Manuel A. d'Abreu Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] T. Basil Smith , W. A. Moorman , T. Dang The IBM S/390 Sysplex Timer. [Citation Graph (0, 0)][DBLP ] Conf ] Steven D. Millman , Edward J. McCluskey Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Verreault , El Mostapha Aboulhamid , Younès Karkouri Multiple Fault Analysis Using a Fault Dropping Technique. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Rennels , Hyeongil Kim VLSI Implementation of a Self-Checking Self-Exercising Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Yuval Tamir , M. Liang , T. Lai , Marc Tremblay The UCLA Mirror Processor: A Building Block for Self-Checking Self-Repring Computing Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Chieh Chang , Kang G. Shin Load Sharing in Hypercube Multicomputers in the Presence of Node Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Vincenzo Grassi Cost Effectiveness Analysis of Different Fault Tolerance Strategies for Hypercube Systems. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Peterson , Jesus O. Tuazon , E. T. Upchurch An Evaluation of Fault-Tolerant Hypercube Architectures for Onboard Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Anindo Bagchi , S. Louis Hakimi An Optimal Algorithm for Distributed System Level Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald P. Bianchini Jr. , Richard W. Buskens An Adaptive Distributed System-Level Diagnosis Algorithm and Its Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Sampath Rangarajan , Donald S. Fussell Probabilistic Diagnosis Algorithms Tailored to System Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory F. Sullivan , Gerald M. Masson Certitication Trails for Data Structures. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Bakken , Richard D. Schlichting Tolerating Failures in the Bag-of-Tasks Programming Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] R. Jagannathan , Edward A. Ashcroft Fault Tolerance in Parallel Implementations of Functional Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan S. Chlebus , Krzysztof Diks , Andrzej Pelc Optimal Broadcasting in Faulty Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Jianli Sun , Jan Gecsei A Multiple-Fault Tolerant Sorting Network. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng , Po-Jen Chuang Fault-Tolerant Gamma Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Dutt , John P. Hayes Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] P. Ramathan , Kang G. Shin A Multiple Copy Approach for Delivering Messages Under Deadline Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] B. E. Aupperle , John F. Meyer State Space Generation for Degradable Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Schuette , John Paul Shen Exploiting Instruction-Level Resource Parallelism for Transparent, Integrated Control-Flow Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Kent D. Wilken Optimal Signature Placement for Process-Error Detection Using Signature Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] T. Michel , Régis Leveugle , Gabriele Saucier A New Approach to Control Flow Checking Without Program Modification. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Cherkassky , Reza Rooholamini , Hossein Lari-Najafi Fault-Tolerant Communications Processing. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. Rezaul Islam , Hany H. Ammar Performability Analysis of Distributed Real-Time Systems with Repetitive Task Invocation. [Citation Graph (0, 0)][DBLP ] Conf ] David V. Pitts The RM Recovery Services. [Citation Graph (0, 0)][DBLP ] Conf ] Erhard Rahm Recovery Concepts for Data Sharing Systems. [Citation Graph (2, 0)][DBLP ] Conf ] Sulaiman Al-Bassam , Bella Bose , Ramarathnam Venkatesan Burst and Unidirectional Error Detecting Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Franklin , Kewal K. Saluja Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC. [Citation Graph (0, 0)][DBLP ] Conf ] C. L. Chen , L. E. Grosbach Fault-Tolerant Memory Design in the IBM Application System/400. [Citation Graph (0, 0)][DBLP ] Conf ] A. L. Narasimha Reddy , Prithviraj Banerjee Gracefully Degradable Disk Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Pascale Thévenod-Fosse , Hélène Waeselynck , Yves Crouzet An Experimental Study on Software Structural Testing: Deterministic versus Random Input Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Echtle , Yinong Chen Evaluation of Deterministic Fault Injection for Fault-Tolerant Protocol Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas S. Bowen , Dhiraj K. Pradhan Program Fault Tolerance Based on Memory Access Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. Iacoponi , S. F. McDonald Distributed Reconfiguration and Recovery in the Advanced Architecture On-Board Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas M. Blough On the Reconfiguration of Memory Arrays Containing Clustered Faults. [Citation Graph (0, 0)][DBLP ] Conf ] C. Chen , An Feng , Tohru Kikuno , Koji Torii Reconfiguration Algorithm for Fault-Tolerant Arrays with Minimum Number of Dangerous Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Myron Hecht , J. Agron , Herbert Hecht , K. H. Kim A Distributed Fault Tolerant Architecture for Nuclear Reactor and Other Critical Process Control Applications. [Citation Graph (0, 0)][DBLP ] Conf ] K. H. Kim , W. J. Guan , Andreas Damm , J. A. Rohr Approaches to Design of Temporary Blackout Handling Capabilities and an Evaluation with a Real-Time Tightly Coupled Network Testbed. [Citation Graph (0, 0)][DBLP ] Conf ] Amer Saeed , Rogério de Lemos , Tom Anderson The Role of Formal Methods in the Requirements Analysis of Safety-Critical Systems: A Train Set Example. [Citation Graph (0, 0)][DBLP ] Conf ] Nitin H. Vaidya , Dhiraj K. Pradhan System Level Diagnosis: Combining Detection and Location. [Citation Graph (0, 0)][DBLP ] Conf ] J. Xu The t/(n-1)-Diagnosability and Its Applications to Fault Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Bapiraju Vinnakota , Niraj K. Jha Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] 