Conferences in DBLP
Joel Grodstein , Rachid Rayess , Tad Truex , Linda Shattuck , Sue Lowell , Dan Bailey , David Bertucci , Gabriel P. Bischoff , Daniel E. Dever , Mike Gowan , Roy Lane , Brian Lilly , Krishna Nagalla , Rahul Shah , Emily Shriver , Shi-Huang Yin , Shannon V. Morton Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:1-6 [Conf ] Vassilis Paliouras , Alexander Skavantzos , Thanos Stouraitis Multi-voltage low power convolvers using the polynomial residue number system. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:7-11 [Conf ] Andrey V. Mezhiba , Eby G. Friedman Properties of on-chip inductive current loops. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:12-17 [Conf ] Monica Donno , Luca Macchiarulo , Alberto Macii , Enrico Macii , Massimo Poncino Enhanced clustered voltage scaling for low power. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:18-23 [Conf ] Victor V. Zyuban Unified architecture level energy-efficiency metric. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:24-29 [Conf ] Ruchir Puri , David S. Kung , Anthony D. Drumm Fast and accurate wire delay estimation for physical synthesis of large ASICs. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:30-36 [Conf ] Kaveh Shakeri , James D. Meindl A compact delay model for series-connected MOSFETs. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:37-40 [Conf ] Jun Chen , Lei He A decoupling method for analysis of coupled RLC interconnects. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:41-46 [Conf ] Volkan Kursun , Eby G. Friedman Low swing dual threshold voltage domino logic. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:47-52 [Conf ] Paolo Azzoni , Andrea Fedeli , Franco Fummi , Graziano Pravadelli , Umberto Rossi , Franco Toto An error simulation based approach to measure error coverage of formal properties. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:53-58 [Conf ] Alessandro Fin , Franco Fummi Protected IP-core test generation. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:59-64 [Conf ] Arun Krishnamachary , Jacob A. Abraham Test generation for resistive opens in CMOS. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:65-70 [Conf ] Ilya Levin , Vladimir Ostrovsky , Sergey Ostanin , Mark G. Karpovsky Self-checking sequential circuits with self-healing ability. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:71-76 [Conf ] Dan Zhao , Shambhu J. Upadhyaya , Martin Margala Minimizing concurrent test time in SoC's by balancing resource usage. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:77-82 [Conf ] Boris D. Andreev , Eby G. Friedman , Edward L. Titlebaum Efficient implementation of a complex ±1 multiplier. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:83-88 [Conf ] Tong Zhang , Keshab K. Parhi On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:89-93 [Conf ] Robert K. Grube , Qi Wang , Sung-Mo Kang Design limitations in deep sub-0.1µm CMOS SRAM. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:94-97 [Conf ] Georgi Kuzmanov , Stamatis Vassiliadis Reconfigurable repetitive padding unit. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:98-103 [Conf ] Paul I. Pénzes , Alain J. Martin Energy-delay efficiency of VLSI computations. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:104-111 [Conf ] Himanshu Kaul , Dennis Sylvester , David Blaauw Active shields: a new approach to shielding global wires. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:112-117 [Conf ] Falah R. Awwad , Mohamed Nekili Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:118-123 [Conf ] Sungbae Hwang , Jacob A. Abraham Selective-run built-in self-test using an embedded processor. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:124-129 [Conf ] Xiaoyu Song , William N. N. Hung , Alan Mishchenko , Malgorzata Chrzanowska-Jeske , Alan J. Coppola , Andrew A. Kennings Board-level multiterminal net assignment. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:130-135 [Conf ] Timothy W. O'Neil , Edwin Hsing-Mean Sha Minimizing resources in a repeating schedule for a split-node data-flow graph. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:136-141 [Conf ] John A. Nestor A new look at hardware maze routing. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:142-147 [Conf ] Qinwei Xu , Pinaki Mazumder Novel interconnect modeling by using high-order compact finite difference methods. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:148-152 [Conf ] Michiel De Wilde , Dirk Stroobandt , Jan Van Campenhout AQUASUN : adaptive window query processing in CAD applications for physical design and verification. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:153-159 [Conf ] Yi Feng , Eduard Cerny Term ordering problem on MDG. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:160-165 [Conf ] J. M. P. Langlois , Dhamin Al-Khalili A low power direct digital frequency synthesizer with 60 dBc spectral purity. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:166-171 [Conf ] Rong Lin , Martin Margala Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:172-177 [Conf ] Whitney J. Townsend , Mitchell A. Thornton , Rolf Drechsler , D. Michael Miller Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:178-183 [Conf ]