Conferences in DBLP
Dimitrios Karayiannis , Spyros Tragoudas Uniform area timing-driven circuit implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Poirot , Gerard Tarroux , Ramine Roane Optimization using implicit techniques for industrial designs. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Hinsberger , Reiner Kolla Optimal technology mapping for single output cells. [Citation Graph (0, 0)][DBLP ] Conf ] D. J. Klein , M. L. Manwaring A Differential Model Approach To Analog Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] E. Penn , L. Schelovanov A new approach for modeling and optimization of analog systems. [Citation Graph (0, 0)][DBLP ] Conf ] B. A. Alhalabi , Magdy A. Bayoumi A scalable analog architecture for neural networks with on-chip learning and refreshing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Sheliga , Edwin Hsing-Mean Sha Bus minimization and scheduling of multi-chip systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph L. Ganley , James P. Cohoon Thumbnail rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP ] Conf ] James M. Varanelli , James P. Cohoon A two-stage simulated annealing methodology. [Citation Graph (0, 0)][DBLP ] Conf ] J. T. Mowchenko , Y. Yang Optimizing wiring space in slicing floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Macii , Massimo Poncino Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. [Citation Graph (0, 0)][DBLP ] Conf ] Nestoras Tzartzanis , William C. Athas Design and analysis of a low-power energy-recovery adder. [Citation Graph (0, 0)][DBLP ] Conf ] Mircea R. Stan , Wayne P. Burleson Coding a terminated bus for low power. [Citation Graph (0, 0)][DBLP ] Conf ] I. S. Abu-Khater , A. Bellaouar , Mohamed I. Elmasry , Ran-Hong Yan Circuit/architecture for low-power high-performance 32-bit adder. [Citation Graph (0, 0)][DBLP ] Conf ] Chuck Monahan , Forrest Brewer Symbolic execution of data paths. [Citation Graph (0, 0)][DBLP ] Conf ] M. Esen Tuna , Kamlesh Rath , Steven D. Johnson Specification and synthesis of bounded indirection. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Hollander , Bradley S. Carlson , Toby D. Bennett Synthesis of SEU-tolerant ASICs using concurrent error correction. [Citation Graph (0, 0)][DBLP ] Conf ] Jayesh Siddhiwala , Liang-Fang Chao Scheduling conditional data-flow graphs with resource sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Yatin Vasant Hoskote , Jacob A. Abraham , Donald S. Fussell Automated verification of temporal properties specified as state machines in VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Zijian Zhou , Xiaoyu Song , Francisco Corella , Eduard Cerny , Michel Langevin Partitioning transition relations efficiently and automatically. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Macii , Massimo Poncino Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos G. Bourbakis , Mohammad Mortazavi An efficient building block layout methodology for compact placement. [Citation Graph (0, 0)][DBLP ] Conf ] Habib Youssef , Sadiq M. Sait , Khaled Nassar , Muhammad S. T. Benten Performance driven standard-cell placement using the genetic algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Ines Peters , Paul Molitor Priority driven channel pin assignment. [Citation Graph (0, 0)][DBLP ] Conf ] N. Ranganathan , K. B. Doreswamy A systolic algorithm and architecture for image thinning. [Citation Graph (0, 0)][DBLP ] Conf ] Garth Baulch , David Hemmendinger , Cherrice Traver Analyzing and verifying locally clocked circuits with the concurrency workbench. [Citation Graph (0, 0)][DBLP ] Conf ] Jae-Tack Yoo , Erik Brunvand , Kent F. Smith Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Seokjin Kim , Ramalingam Sridhar A local clocking approach for self-timed datapath designs. [Citation Graph (0, 0)][DBLP ] Conf ] Vincenzo Catania , N. Fiorito , Michele Malgeri , Marco Russo A soft computing approach to hardware software codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Stanley Habib , Quan Xu Technology mapping algorithms for sequential circuits using look-up table based FPGAS. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Assi , Bozena Kaminska Modeling of communication protocols in VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. van der Westhuizen , R. G. Harley , D. C. Levy , D. R. Woodward Using EDIF for software generation. [Citation Graph (0, 0)][DBLP ] Conf ] Hon F. Li , P. N. Lam A protocol extraction strategy for control point insertion in design for test of transition signaling circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zaifu Zhang , Robert D. McLeod , G. E. Bridges Statistical estimation of delay fault detectabilities and fault grading. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Zheng , Kewal K. Saluja , Rajiv Jain Test application time reduction for scan based sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anne-lise Courbis , Jean François Santucci Pseudo-random behavioral ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Manjit Borah , Robert Michael Owens , Mary Jane Irwin Fast algorithm for performance-oriented Steiner routing. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony D. Johnson On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasa R. Danda , Sreekrishna Madhwapathy , Naveed A. Sherwani , A. Sureka OPRON: a new approach to planar OTC routing. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Khanna , Shaodi Gao , Krishnaiyan Thulasiraman Parallel hierarchical global routing for general cell layout. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhao , Nicole Marie Sabine , Edwin Hsing-Mean Sha Improving self-timed pipeline ring performance through the addition of buffer loops. [Citation Graph (0, 0)][DBLP ] Conf ] O. A. Petlin , Stephen B. Furber Scan testing of asynchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Pastor , Jordi Cortadella , Oriol Roig A new look at the conditions for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] L. F. Fuller , C. Kraaijenvanger Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT. [Citation Graph (0, 0)][DBLP ] Conf ] Hardy J. Pottinger , Chien-Yuh Lin Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Pearson Linking fabrication and parametric testing to VLSI design courses. [Citation Graph (0, 0)][DBLP ] Conf ] Wallace B. Leigh A personal computer based VLSI design curriculum. [Citation Graph (0, 0)][DBLP ] Conf ] A. Agrawal , A. Raju , S. Varadarajan , Magdy A. Bayoumi A scalable shared buffer ATM switch architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Pong P. Chu ATM burst traffic generator. [Citation Graph (0, 0)][DBLP ] Conf ] W. H. F. J. Körver A universal formalization of the effects of threshold voltages for discrete switch-level circuit models. [Citation Graph (0, 0)][DBLP ] Conf ] 