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Conferences in DBLP

ACM Great Lakes Symposium on VLSI (glvlsi)
2006 (conf/glvlsi/2006)

  1. Dan Page, Jamil Kawa, Charles Chiang
    DFM: swimming upstream. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:1- [Conf]
  2. Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour
    Design approaches for hybrid CMOS/molecular memory based on experimental device data. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:2-7 [Conf]
  3. Rui Zhang, Niraj K. Jha
    Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:8-13 [Conf]
  4. Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal
    Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:14-18 [Conf]
  5. Kiran Puttaswamy, Gabriel H. Loh
    Thermal analysis of a 3D die-stacked high-performance microprocessor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:19-24 [Conf]
  6. Young-Jun Kim, Taewhan Kim
    HW/SW partitioning techniques for multi-mode multi-task embedded applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:25-30 [Conf]
  7. Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino
    ISS-centric modular HW/SW co-simulation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:31-36 [Conf]
  8. Ozcan Ozturk, Mahmut T. Kandemir, Suleyman Tosun
    An ILP based approach to address code generation for digital signal processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:37-42 [Conf]
  9. Daniel Große, Ulrich Kühne, Rolf Drechsler
    HW/SW co-verification of embedded systems using bounded model checking. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:43-48 [Conf]
  10. Rui Tang, Yong-Bin Kim
    PWAM signalling scheme for high speed serial link transceiver design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:49-52 [Conf]
  11. Hung Tien Bui, Yvon Savaria
    High speed differential pulse-width control loop based on frequency-to-voltage converters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:53-56 [Conf]
  12. Abhishek Jajoo, Michael Sperling, Tamal Mukherjee
    Synthesis of a wideband low noise amplifier. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:57-62 [Conf]
  13. Minghai Li, Fei Yuan
    A 0.13µm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:63-66 [Conf]
  14. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    Dominator-based partitioning for delay optimization. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:67-72 [Conf]
  15. Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
    How does partitioning matter for 3D floorplanning? [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:73-78 [Conf]
  16. Chang Woo Kang, Massoud Pedram
    Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:79-84 [Conf]
  17. Royce L. S. Ching, Evangeline F. Y. Young
    Shuttle mask floorplanning with modified alpha-restricted grid. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:85-90 [Conf]
  18. Xiangyuan Liu, Shuming Chen
    Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:91-94 [Conf]
  19. Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli
    A simulation methodology for reliability analysis in multi-core SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:95-99 [Conf]
  20. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Power density minimization for highly-associative caches in embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:100-104 [Conf]
  21. Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud
    An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:105-110 [Conf]
  22. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:111-114 [Conf]
  23. Zuying Luo
    General transistor-level methodology on VLSI low-power design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:115-118 [Conf]
  24. K. Najeeb, Vishal Gupta, V. Kamakoti
    Delay and peak power minimization for on-chip buses using temporal redundancy. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:119-122 [Conf]
  25. Zhiyuan Li, FengChang Lai, Mingyan Yu
    Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:123-126 [Conf]
  26. Fei Yuan
    A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:127-130 [Conf]
  27. Jun-Da Chen, Zhi-Ming Lin
    A low-power and high-linear double-balanced switching mixer. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:131-134 [Conf]
  28. Yarallah Koolivand, Omid Shoaei, A. Fotowat-Ahmadi, Ali Zahabi, Parviz Jabedar-Maralani
    Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:135-139 [Conf]
  29. Qianneng Zhou, FengChang Lai, Mingyan Yu
    On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chips. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:140-143 [Conf]
  30. Hung D. Nguyen, Benjamin J. Blalock, Suheng Chen
    A SiGe BiCMOS linear regulator with wideband, high power supply rejection. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:144-148 [Conf]
  31. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Optimizing noise-immune nanoscale circuits using principles of Markov random fields. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:149-152 [Conf]
  32. Kiran Puttaswamy, Gabriel H. Loh
    Dynamic instruction schedulers in a 3-dimensional integration technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:153-158 [Conf]
  33. Song Peng, Rajit Manohar
    Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:159-164 [Conf]
  34. William R. Roberts, Dimitrios Velenis
    Effects of process and environmental variations on timing characteristics of clocked registers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:165-168 [Conf]
  35. Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya
    On finding the minimum test set of a BDD-based circuit. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:169-172 [Conf]
  36. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
    Maximum effective distance of on-chip decoupling capacitors in power distribution grids. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:173-179 [Conf]
  37. Bo Shen, Sunil P. Khatri, Takis Zourntos
    Implementation of MOSFET based capacitors for digital applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:180-186 [Conf]
  38. Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud
    Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:187-191 [Conf]
  39. Jonathan Rosenfeld, Eby G. Friedman
    Sensitivity evaluation of global resonant H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:192-197 [Conf]
  40. Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
    2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:198-203 [Conf]
  41. Sergio Tota, Mario R. Casu, Luca Macchiarulo
    Implementation analysis of NoC: a MPSoC trace-driven approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:204-209 [Conf]
  42. Jeff Parkhurst
    From single core to multi-core to many core: are we ready for a new exponential? [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:210- [Conf]
  43. Hosung (Leo) Kim, John Lillis, Milos Hrkic
    Techniques for improved placement-coupled logic replication. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:211-216 [Conf]
  44. Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
    A design flow to optimize circuit delay by using standard cells and PLAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:217-222 [Conf]
  45. Andrew B. Kahng, Bao Liu, Xu Xu
    Statistical gate delay calculation with crosstalk alignment consideration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:223-228 [Conf]
  46. Joonsoo Kim, Michael Orshansky
    Towards formal probabilistic power-performance design space exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:229-234 [Conf]
  47. Chuen-Song Chen, Jien-Chung Lo, Tian Xia
    An indirect current sensing technique for IDDQ and IDDT tests. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:235-240 [Conf]
  48. Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer
    SACI: statistical static timing analysis of coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:241-246 [Conf]
  49. Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich
    Performance verification of high-performance ASICs using at-speed structural test. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:247-252 [Conf]
  50. Shahin Nazarian, Ali Iranli, Massoud Pedram
    Crosstalk analysis in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:253-258 [Conf]
  51. Talal Bonny, Jörg Henkel
    Using Lin-Kernighan algorithm for look-up table compression to improve code density. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:259-265 [Conf]
  52. Hima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell
    FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:266-271 [Conf]
  53. Xinmiao Zhang
    Partial parallel factorization in soft-decision Reed-Solomon decoding. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:272-277 [Conf]
  54. Ali Bastani, Charles A. Zukowski
    Monotonic static CMOS tradeoffs in sub-100nm technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:278-283 [Conf]
  55. Vahid Majidzadeh, Omid Shoaei
    A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:284-289 [Conf]
  56. Wei-Chung Cheng, Chain-Fu Chao
    Perception-guided power minimization for color sequential displays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:290-295 [Conf]
  57. Zhonghai Lu, Mingchen Zhong, Axel Jantsch
    Evaluation of on-chip networks using deflection routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:296-301 [Conf]
  58. Lun Li, Mitchell A. Thornton, David W. Matula
    A digit serial algorithm for the integer power operation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:302-307 [Conf]
  59. Scott J. Campbell, Sunil P. Khatri
    Resource and delay efficient matrix multiplication using newer FPGA devices. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:308-311 [Conf]
  60. Yongmei Dai, Zhiyuan Yan, Ning Chen
    Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:312-315 [Conf]
  61. Bo Fu, Qiaoyan Yu, Paul Ampadu
    Energy-delay minimization in nanoscale domino logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:316-319 [Conf]
  62. Luciano Volcan Agostini, Roger Porto, Sergio Bampi, Leandro Rosa, José Güntzel, Ivan Saraiva Silva
    High throughput architecture for H.264/AVC forward transforms block. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:320-323 [Conf]
  63. Sathish Chandra, Francesco Regazzoni, Marcello Lajolo
    Hardware/software partitioning of operating systems: a behavioral synthesis approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:324-329 [Conf]
  64. Mohamed H. Zaki, Sofiène Tahar, Guy Bois
    A practical approach for monitoring analog circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:330-335 [Conf]
  65. Xu Zhang, Xiaohong Jiang, Susumu Horiguchi
    A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:336-340 [Conf]
  66. Jinwen Xi, Peixin Zhong
    A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:341-344 [Conf]
  67. Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
    A formal approach for high level synthesis of linear analog systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:345-348 [Conf]
  68. Renqiu Huang, Ranga Vemuri
    Transformation synthesis for data intensive applications to FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:349-352 [Conf]
  69. Mohamed El-Nozahi, Yehia Massoud
    An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:353-356 [Conf]
  70. Marios Kalathas, Dimitrios Voudouris, George K. Papakonstantinou
    A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functions. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:357-361 [Conf]
  71. Heon-Mo Koo, Prabhat Mishra
    Test generation using SAT-based bounded model checking for validation of pipelined processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:362-365 [Conf]
  72. I-Lun Tseng, Adam Postula
    An efficient algorithm for partitioning parameterized polygons into rectangles. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:366-371 [Conf]
  73. Murari Mani, Mahesh Sharma, Michael Orshansky
    Application of fast SOCP based statistical sizing in the microprocessor design flow. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:372-375 [Conf]
  74. Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching
    Block alignment in 3D floorplan using layered TCG. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:376-380 [Conf]
  75. Paul Sotiriadis, Abdullah Celik, Zhaonian Zhang
    Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modeling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:381-385 [Conf]
  76. Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy
    Selective code/data migration for reducing communication energy in embedded MpSoC architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:386-391 [Conf]
  77. Changjiu Xian, Yung-Hsiang Lu
    Dynamic voltage scaling for multitasking real-time systems with uncertain execution time. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:392-397 [Conf]
  78. Xiangrong Zhou, Peter Petrov
    Low-power cache organization through selective tag translation for embedded processors with virtual memory support. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:398-403 [Conf]
  79. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    STV-Cache: a leakage energy-efficient architecture for data caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:404-409 [Conf]
  80. Ranjith Kumar, Volkan Kursun
    A design methodology for temperature variation insensitive low power circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:410-415 [Conf]
  81. Giby Samson, Lawrence T. Clark
    Circuit architecture for low-power race-free programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:416-421 [Conf]
  82. Qingli Zhang, Jinxiang Wang, Yizheng Ye
    An energy-efficient temporal encoding circuit technique for on-chip high performance buses. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:422-427 [Conf]
  83. Zhiyu Liu, Volkan Kursun
    Leakage current starved domino logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:428-433 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002