Conferences in DBLP
Y. Takei , A. Onozawat , K. Kawaitt , H. Kitazawa An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:2-7 [Conf ] Elizabeth J. Brauer , Pradeep Elamanchili A Full-Swing Bootstrapped BiCMOS Buffer. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:8-13 [Conf ] João Navarro Jr. , Reinaldo Silveira , Fábio L. Romao , Wilhelmus A. M. Van Noije A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:14-0 [Conf ] Irith Pomeranz , Sudhakar M. Reddy On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:20-25 [Conf ] Musaed A. Al-Kharji , Sami A. Al-Arian A New Heuristic Algorithm for Estimating Signal and Detection Probabilities. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:26-31 [Conf ] Cristiana Bolchini , Fabio Salice , Donatella Sciuto Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:32-0 [Conf ] Hiroshi Sawada , Shigeru Yamashita , Akira Nagoya Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:39-44 [Conf ] Andreas G. Veneris , Ibrahim N. Hajj A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:45-50 [Conf ] Josef Fleischmann , Rolf Schlagenhaft , Martin Peller , Norbert Fröhlich OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:51-0 [Conf ] Adel Baganne , Jean Luc Philippe , Eric Martin Hardware interface design for real time embedded systems. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:58-63 [Conf ] Julio Leao da Silva Jr. , Chantal Ykman-Couvreur , Bill Lin , Hugo De Man , Gjalt G. de Jong A System Design Methodology for Telecommunication Network Applications. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:64-69 [Conf ] Antonio Lioy , Enrico Macii , Massimo Poncino , Massimo Rossello Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:70-0 [Conf ] Luca Benini , Giovanni De Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:77-82 [Conf ] Shaoyi Wang Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:83-85 [Conf ] Hanho Lee , Gerald E. Sobelman A New Low-Voltage Full Adder Circuit. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:88-0 [Conf ] Fabio Ancona , Giorgio Oddone , Stefano Rovetta , Gianni Uneddu , Rodolfo Zunino VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:94-99 [Conf ] Sam S. Appleton , Shannon V. Morton , Michael J. Liebelt A new method for asynchronous pipeline control. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:100-104 [Conf ] Kevin P. Acken , Eric Gayles , Thomas P. Kelliher , Robert Michael Owens , Mary Jane Irwin The MGAP Family of Processor Arrays. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:105-0 [Conf ] H.-Ch. Dahmen , Uwe Gläser , Heinrich Theodor Vierhaus An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:112-117 [Conf ] Franco Fummi , Mariagiovanna Sami , F. Tartarini Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:118-123 [Conf ] Giacomo Buonanno , Fabrizio Ferrandi , L. Ferrandi , Franco Fummi , Donatella Sciuto How an "Evolving" Fault Model Improves the Behavioral Test Generation. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:124-0 [Conf ] Michael Weeks , M. B. Maaz , H. Krishnamurthy , Paul Shipley , Magdy A. Bayoumi A prototype chipset for a large scaleable ATM switching node. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:131-136 [Conf ] Elizabeth J. Brauer , Ranu Jung , Denise M. Wilson , James J. Abbas Analog Circuit Model of Lamprey Unit Pattern Generator. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:137-142 [Conf ] Ali Assi , Mohamad Sawan , Rabin Raut A New CMOS Tunable Transconductor Dedicated to VHF Continuous-Time Filters. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:143-0 [Conf ] Sissades Tongsima , Chantana Chantrapornchai , Edwin Hsing-Mean Sha , Nelson L. Passos Scheduling with Confidence for Probabilistic Data-flow Graphs. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:150-155 [Conf ] Raghava V. Cherabuddi , Magdy A. Bayoumi , H. Krishnamurthy A low power based system partitioning and binding technique for multi-chip module architectures. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:156-162 [Conf ] Ted Zhihong Yu , Edwin Hsing-Mean Sha , Nelson L. Passos , Roy Dz-Ching Ju Algorithm and Hardware Support for Branch Anticipation. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:163-0 [Conf ] Sergio D'Angelo , Lauro Mantoani , Riccardo P. G. Mazzei , Stefania Russo , Giacomo R. Sechi Modular Design of Communication Node Prototypes. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:170-175 [Conf ] Fabio Ancona , Alessandro De Gloria , Rodolfo Zunino Parallel VLSI Architectures for Cryptographic Systems. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:176-181 [Conf ] Eric Gayles , Kevin P. Acken , Robert Michael Owens , Mary Jane Irwin A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:182-0 [Conf ]