Conferences in DBLP
Chris Coulston Constructing exact octagonal steiner minimal trees. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini , Lawrence T. Pileggi , Andrzej J. Strojwas Bounding the efforts on congestion optimization for physical synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Weidong Wang , Tat Kee Tan , Jiong Luo , Yunsi Fei , Li Shang , Keith S. Vallerio , Lin Zhong , Anand Raghunathan , Niraj K. Jha A comprehensive high-level synthesis system for control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP ] Conf ] Saied Hemati , Amir H. Banihashemi Iterative decoding in analog CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari Design issues in low-voltage high-speed current-mode logic buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy A. El-Moursy , Eby G. Friedman Optimum wire sizing of RLC interconnect with repeaters. [Citation Graph (0, 0)][DBLP ] Conf ] Roy Mader , Ivan S. Kourtev Reduced dynamic swing domino logic. [Citation Graph (0, 0)][DBLP ] Conf ] Chao You , Jong-Ru Guo , Russell P. Kraft , Kuan Zhou , Michael Chu , John F. McDonald A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Salim Maza , Mónico Linares Aranda Interconnected rings and oscillators as gigahertz clock distribution nets. [Citation Graph (0, 0)][DBLP ] Conf ] Paul-Peter Sotiriadis Information storage capacity of crossbar switching networks. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Beckett Exploiting multiple functionality for nano-scale reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jincheol Yoo , Kyusun Choi , Jahan Ghaznavi CMOS flash analog-to-digital converter for high speed and low voltage applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nadine Gergel , Shana Craft , John Lach Modeling QCA for area minimization in logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Di , Jiann S. Yuan Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. [Citation Graph (0, 0)][DBLP ] Conf ] Menahem Lowy , Neal Butler , Rosanne Tinkler Low power VLSI sequential circuit architecture using critical race control. [Citation Graph (0, 0)][DBLP ] Conf ] Aiyappan Natarajan , David Jasinski , Wayne Burleson , Russell Tessier A hybrid adiabatic content addressable memory for ultra low-power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Timm Ostermann , Bernd Deutschmann TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Junhao Shi , Görschwin Fey MuTaTe: an efficient design for testability technique for multiplexor based circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsee K. Pamula , Krishnendu Chakrabarty Cooling of integrated circuits using droplet-based microfluidics. [Citation Graph (0, 0)][DBLP ] Conf ] Fang Wang , Sofiène Tahar Language emptiness checking using MDGs. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Palermo , Cristina Silvano , S. Valsecchi , Vittorio Zaccaria A system-level methodology for fast multi-objective design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Arindam Mukherjee , Krishna Reddy Dusety , Rajsaktish Sankaranarayan A practical CAD technique for reducing power/ground noise in DSM circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chandrasekar Rajagopal , Karthik Sridhar , Adrian Nunez RF CMOS circuit optimizing procedure and synthesis tool. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Chiang , Qing Su , Ching-Shoei Chiang Wirelength reduction by using diagonal wire. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoning Qi , Goetz Leonhardt , Daniel Flees , Xiao-Dong Yang , Sangwoo Kim , Stephan Mueller , Hendrik Mau , Lawrence T. Pileggi A fast simulation approach for inductive effects of VLSI interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Woo Kang , Soroush Abbaspour , Massoud Pedram Buffer sizing for minimum energy-delay product by using an approximating polynomial. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Igor L. Markov , Karem A. Sakallah FORCE: a fast and easy-to-implement variable-ordering heuristic. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura Routing methodology for minimizing 1nterconnect energy dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Jiwei Chen , Bingxue Shi Circuit design of a wide tuning range CMOS VCO with automatic amplitude control. [Citation Graph (0, 0)][DBLP ] Conf ] Li Yang , J. S. Yuan A decoupling technique for CMOS strong-coupled structures. [Citation Graph (0, 0)][DBLP ] Conf ] Ilias Tagkopoulos , Charles A. Zukowski , German Cavelier , Dimitris Anastassiou A custom FPGA for the simulation of gene regulatory networks. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii , Elvira Omerbegovic , Massimo Poncino , Fabrizio Pro A novel architecture for power maskable arithmetic units. [Citation Graph (0, 0)][DBLP ] Conf ] John Mayega , Okan Erdogan , Paul M. Belemjian , Kuan Zhou , John F. McDonald , Russell P. Kraft 3D direct vertical interconnect microprocessors test vehicle. [Citation Graph (0, 0)][DBLP ] Conf ] Adarsh K. Jain , Lin Yuan , Pushkin R. Pari , Gang Qu Zero overhead watermarking technique for FPGA designs. [Citation Graph (0, 0)][DBLP ] Conf ] Geoff Knagge , David Garrett , Sivarama Venkatesan , Chris Nicol Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Rajkiran Gottumukkal , Vijayan K. Asari System level design of real time face recognition architecture based on composite PCA. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhua Gan , Shouli Yan , Jacob A. Abraham Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy A. El-Moursy , Eby G. Friedman Shielding effect of on-chip interconnect inductance. [Citation Graph (0, 0)][DBLP ] Conf ] Bhushan A. Shinkre , James E. Stine A pipelined clock-delayed domino carry-lookahead adder. [Citation Graph (0, 0)][DBLP ] Conf ] Atanu Chattopadhyay , Zeljko Zilic A globally asynchronous locally dynamic system for ASICs and SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael I. Fuller , James P. Mabry , John A. Hossack , Travis N. Blalock 40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications. [Citation Graph (0, 0)][DBLP ] Conf ] Shyam Ramji , Nagu R. Dhanwada Design topology aware physical metrics for placement analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Bharat Krishna , C. Y. Roger Chen , Naresh Sehgal A novel ultra-fast heuristic for VLSI CAD steiner trees. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Macii , Massimo Poncino , Sabino Salerno Combining wire swapping and spacing for low-power deep-submicron buses. [Citation Graph (0, 0)][DBLP ] Conf ] Eric S. H. Wong , Evangeline F. Y. Young , Wai-Kei Mak Clustering based acyclic multi-way partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Tang , Hui Zhang , Alex Doboli Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing. [Citation Graph (0, 0)][DBLP ] Conf ] Ameya R. Agnihotri , Patrick H. Madden Congestion reduction in traditional and new routing architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , N. Ranganathan , Sunil K. Chappidi Simultaneous peak and average power minimization during datapath scheduling for DSP processors. [Citation Graph (0, 0)][DBLP ] Conf ] Noureddine Chabini , Ismaïl Chabini , El Mostapha Aboulhamid , Yvon Savaria Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Palermo , Mariagiovanna Sami , Cristina Silvano , Vittorio Zaccaria , Roberto Zafalon Branch prediction techniques for low-power VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Boris D. Andreev , Edward L. Titlebaum , Eby G. Friedman Orthogonal code generator for 3G wireless transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-seon Cho , Jong-on Park , Jin-seok Hong , Goang-seog Choi 54x54-bit radix-4 multiplier based on modified booth algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan Abdul-Aziz Gutub , Mohammad K. Ibrahim Power-time flexible architecture for GF(2k ) elliptic curve cryptosystem computation. [Citation Graph (0, 0)][DBLP ] Conf ] Yeshwant Kolla , Yong-Bin Kim , John Carter A novel 32-bit scalable multiplier architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yanni Chen , Keshab K. Parhi High throughput overlapped message passing for low density parity check codes. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Merlo , Kwang-Hyun Baek , Myung-Jun Choe Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers. [Citation Graph (0, 0)][DBLP ] Conf ] Jung-Lin Yang , Erik Brunvand Using dynamic domino circuits in self-timed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Grassert , Dirk Timmermann Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs. [Citation Graph (0, 0)][DBLP ] Conf ] David Harris , Genevieve Breed , Matt Erler , David Diaz Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Emira , Edgar Sánchez-Sinencio Variable gain amplifier with offset cancellation. [Citation Graph (0, 0)][DBLP ] Conf ] Atul Maheshwari , Wayne Burleson Repeater and current-sensing hybrid circuits for on-chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ram Suryanarayan , Anubhav Gupta , Travis N. Blalock A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Yun Cheol Han , Kwang il Kim , Jun Kim , Kwang Sub Yoon A dual band CMOS VCO with a balanced duty cycle buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Jiwei Chen , Bingxue Shi New approach to CMOS current reference with very low temperature coefficient. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed A. Elgamel , Sumeer Goel , Magdy A. Bayoumi Noise tolerant low voltage XOR-XNOR for fast arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Srivaths Ravi On automatic generation of RTL validation test benches using circuit testing techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanouil Kalligeros , Xrysovalantis Kavousianos , Dimitris Nikolos A highly regular multi-phase reseeding technique for scan-based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Guo Coefficient-based parametric faults detection in analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Fin , Franco Fummi , Graziano Pravadelli Mixing ATPG and property checking for testing HW/SW interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] 