Conferences in DBLP
Irith Pomeranz , Sudhakar M. Reddy PASTA: Partial Scan to Enhance Test Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo F. Flores , Horácio C. Neto , João P. Marques Silva On Applying Set Covering Models to Test Set Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Kozo Kinoshita , Seiji Kajihara On Test Generation with A Limited Number of Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Spyros Tragoudas , Maria K. Michael Functional ATPG for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Haridimos T. Vergos , Dimitris Nikolos , Y. Tsiatouhas , Th. Haniotakis , Michael Nicolaidis On Path Delay Fault Testing of Multiplexer - Based Shifters. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Aamir A. Farooqui , Vojin G. Oklobdzija VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Bishop , Thomas P. Kelliher , Mary Jane Irwin The Design of a Register Renaming Unit. [Citation Graph (0, 0)][DBLP ] Conf ] O. Hauck , M. Garg , Sorin A. Huss Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Hilgenstock , Klaus Herrmann , Peter Pirsch Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Janardhan H. Satyanarayana , Keshab K. Parhi Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Hsiang Lu , Giovanni De Micheli Adaptive Hard Disk Power Management on Personal Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Yehea I. Ismail , Eby G. Friedman , José Luis Neves Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Emrah Acar , Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. [Citation Graph (0, 0)][DBLP ] Conf ] Yanhong Yuan , Prithviraj Banerjee ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Ninglong Lu , Ibrahim N. Hajj An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Cornetta , Jordi Cortadella A Radix-16 SRT Division Unit with Speculation of the Quotient Digits. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Luh , John Choma Jr. , Jeffrey T. Draper Area-Efficient Area Pad Design for High Pin-Count Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Masera , Gianluca Piccinini , Massimo Ruo Roth , Maurizio Zamboni New 2 Gbit/s CMOS I/O pads. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Maria Brosa , Joan Figueras On Optimizing Test Strategies for Analog Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Erik A. McShane , Krishna Shenai , Leon Alkalai , E. Kolawa , V. Boyadzhyan , B. Blaes , Wai-Chi Fang Novel Design for Testability of a Mixed-Signal VLSI IC. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Wang , Han Ngee Tan The Development of Analog SPICE Behavioral Model Based on IBIS Model. [Citation Graph (0, 0)][DBLP ] Conf ] Von-Kyoung Kim , Tom Chen , Mick Tegethoff Fault Coverage Estimation for Early Stage of VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Bassam Shaer , Sami A. Al-Arian , David L. Landis Pseudo-Exhaustive Testing of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Janes , R. P. Andres , E. H. Chen , J. Dicke , V. R. Kolagunta , J. Lauterbach , T. Lee , J. Liu , M. R. Melloch , E. L. Peckham , T. Pletcher , R. Reifenberger , H. J. Ueng , B. L. Walsh , J. M. Woodall , C. P. Kubiak , B. Kasibhatla Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael T. Niemier , Peter M. Kogge Logic in Wire: Using Quantum Dots to Implement a Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Árpád Csurgay , Craig S. Lent , Wolfgang Porod Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays? [Citation Graph (0, 0)][DBLP ] Conf ] T. P. E. Broekaert , B. Brar , F. Morris , A. C. Seabaugh , G. Frazier Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Chantana Chantrapornchai , Edwin Hsing-Mean Sha , Xiaobo Sharon Hu Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections. [Citation Graph (0, 0)][DBLP ] Conf ] Ronnie L. Wright , Michael A. Shanblatt Reducing BDD Size by Exploiting Structural Connectivity. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya An Integrated Approach for Synthesizing LUT Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ghosh , Sandeep K. Lodha , Ranga Vemuri Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Sharma , C. P. Ravikumar Design Issues in Synthesis of Reusable Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Masafumi Yamamoto , Hideaki Matsuzaki , Toshihiro Itoh , Takao Waho , T. Akeyoshi , J. Osaka Ultrahigh-Speed Circuits Using Resonant Tunneling Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Hideaki Matsuzaki , Toshihiro Itoh , Masafumi Yamamoto A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Uemura , Pinaki Mazumder Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Fay , Gary H. Bernstein , David H. Chow , J. Schulman , Pinaki Mazumder , W. Williamson , B. K. Gilbert Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Berzon , Terry J. Fountain A Memory Design in QCAs using the SQUARES Formalism. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Pin R. Liu , Jacob A. Abraham Transistor Level Synthesis for Static CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Humberto Llanos Quintero , Marius Strum SINMEF - A Decomposition Based Synthesis Tool for Large FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Li , Zhongwei Xu , Yan Jin An Approach for Testing Safety-Critical Software. [Citation Graph (0, 0)][DBLP ] Conf ] Travis E. Doom , Anthony S. Wojcik , Moon-Jung Chung Design Recovery for Incomplete Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Macii , Enrico Macii , Giuseppe Odasso , Massimo Poncino , Riccardo Scarsi Regression-Based Macromodeling for Delay Estimation of Behavioral Components. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Blythe , Robert A. Walker Efficiently Searching the Optimal Design Space. [Citation Graph (0, 0)][DBLP ] Conf ] Yiu Wu , John Ling , Ward J. Helms A Bandpass Sigma-Delta for Software Low-Power and Low-Voltage Radio by Using PATH Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Seung-Moon Yoo , Sung-Mo Kang No-Race Charge-Recycling Differential Logic (NCDL). [Citation Graph (0, 0)][DBLP ] Conf ] Tuna B. Taram , Mohammed Ismail Linear Transconductors Using Low Voltage Low Power Square-Law Cmos Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Varshavsky , Masayuki Tsukisaka Current Sensor on the Base of Permanent Pre-chargeable Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Navindra Yadav , Michael J. Schulte , John Glossner Parallel Saturating Fractional Arithmetic Units. [Citation Graph (0, 0)][DBLP ] Conf ] Shugang Wei , Kensuke Shimizu Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] H.-Ch. Dahmen , Uwe Gläser , Z. Stamenkovic Modell Evaluation Using Genetic Manipulation Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled M. Elleithy , E. G. Abd-El-Fattah A Genetic Algorithm for Register Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Chakraborty , Natesan Venkateswaran Congestion Mitigation During Placement. [Citation Graph (0, 0)][DBLP ] Conf ] John Karro , James P. Cohoon A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Sae Hwan Kim , Shiu-Kai Chin Formal Verification of Tree-Structured Carry-Lookahead Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Samit Chaudhuri , Robert A. Walker Bounding Algorithms for Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Hoda S. Abdel-Aty-Zohdy , Mahmoud Al-Nsour Digital Neural Processing Unit for Electronic Nose. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaohui Wang , Wolfgang Porod A Low Power Charge-Recycling CMOS Clock Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Hobson , Allan R. Dyck A Multiple-Input Single-Phase Clock Flip-Flop Family. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Lemberski Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Altaf-Ul-Amin , Zahari Mohamed Darus VHDL Design of a Test Processor Based on Mixed-Mode Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jim E. Crenshaw , Majid Sarrafzadeh , Prithviraj Banerjee , Pradeep Prabhakaran An Incremental Floorplanner. [Citation Graph (0, 0)][DBLP ] Conf ] R. Balakrishnan , Richard F. Hobson A Greedy Router with Technology Targetable Output. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Li , Dilip K. Banerji Routability Prediction for Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Chillet , Olivier Sentieys , Michel Corazza Memory Unit Design for Real Time DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Gibson , Carla N. Purdy , Alva Hare , Fred R. Beyette Jr. Design Automation of MEMS Systems Using Behavioral Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Robert L. Ewing Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems. [Citation Graph (0, 0)][DBLP ] Conf ] N. Tayebi , A. K. Tayebi , Y. Belkacemi Numerical Tools for Fracture of MEMS Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Dinos Moundanos , Jacob A. Abraham Formal Checking of Properties in Complex Systems Using Abstractions. [Citation Graph (0, 0)][DBLP ] Conf ] Subhashini Balakrishnan , Sofiène Tahar A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Hendricx , Luc J. M. Claesen Symbolic Multi-Level Verification of Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Levin , Vladimir Sinelnikov Self-Checking of FPGA-Based Control Units. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Yu , Fangmei Wu A Software Acceptance Testing Technique Based on Knowledge Accumulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Chang Kim , Kewal K. Saluja , Vishwani D. Agrawal A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Amr N. Hafez , Mohamed I. Elmasry A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Chulwoo Kim , Seung-Moon Yoo , Sung-Mo Kang NMOS Energy Recovery Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Radu M. Secareanu , Ivan S. Kourtev , Juan Becerra , Thomas E. Watrobski , Christopher Morton , William Staub , Thomas Tellier , Eby G. Friedman Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lim Chu Aun , S. M. Rezaul Hasan An all Digital BiCMOS Phase Lock Loop for VLSI Processors. [Citation Graph (0, 0)][DBLP ] Conf ] José Francisco López , Roberto Sarmiento , Antonio Núñez , Kamran Eshraghian , Stefan Lachowicz , Derek Abbott Low Power Techniques for Digital GaAs VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Amr G. Wassal , M. Anwarul Hasan A VLSI Architecture for ATM Algorithm-Agile Encryption. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Stroobandt On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule. [Citation Graph (0, 0)][DBLP ] Conf ] Erik A. McShane , Krishna Shenai , Leon Alkalai , E. Kolawa , V. Boyadzhyan , B. Blaes , Wai-Chi Fang Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] S. Gailhard , Nathalie Julien , Adel Baganne , Eric Martin Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhiko Kamigata , Koso Murakami , Makoto Iwata , Hiroaki Terada Proposal of Data-Driven Processor Architecture Qv-K1. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Katkoori , Ranga Vemuri Accurate Resource Estimation Algorithms for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Von-Kyoung Kim , Tom Chen Assessing Defect Coverage of Memory Testing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Li , Paul Y. S. Cheung Exploiting Test Resource Optimization in Data Path Synthesis for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Pacha , Peter Glösekötter , Karl Goser , U. Auer , W. Prost , F.-J. Tegude Resonant Tunneling Transistors for Threshold Logic Circuit Applications. [Citation Graph (0, 0)][DBLP ] Conf ] David Crawley A Multilevel Cache Memory Architecture for Nanoelectronics. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante ALPS: A Peak Power Estimation Tool for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Corgnati , Enrico Macii , Massimo Poncino Clustered Table-Based Macromodels for RTL Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuyu Chang , John Choma Jr. , Jack Wills The Design of Cmos Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yuke Wang , Xiaoyu Song , El Mostapha Aboulhamid A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem II. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Komatsu , Makoto Ikeda , Kunihiro Asada Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Hung Lin , Mohammed Ismail A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaopeng Li , Mohammed Ismail A Second-Order Sigma-Delta Modulator with Built-in VGA to Improve SNR and Harmonic Distortion. [Citation Graph (0, 0)][DBLP ] Conf ] R. Shalem , Lizy Kurian John , Eugene John A Novel Low Power Energy Recovery Full Adder Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Memory Chip BIST Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ihn Kim , Craig S. Steele , Jefferey G. Koller A Fully Pipelined, 700MBytes/s DES Encryption Core. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa H. Abd-El-Barr , Yanging Xu , Carl McCrosky Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] James C. Ellenbogen Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Marshall Goodnick , Jonathan P. Bird , David K. Ferry , Allen D. Gunther , Maroun D. Khoury , Michael Kozicki , M. J. Rack , T. J. Thornton , D. Vasileska-Kafedezka Transport in Split Gate MOS Quantum Dot Structures. [Citation Graph (0, 0)][DBLP ] Conf ] 