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Conferences in DBLP

ACM Great Lakes Symposium on VLSI (glvlsi)
2000 (conf/glvlsi/2000)

  1. Vivek De, Shekhar Borkar
    Low power and high performance design challenges in future technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:1-6 [Conf]
  2. Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
    CMOS system-on-a-chip voltage scaling beyond 50nm. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:7-12 [Conf]
  3. Vijay Sundararajan, Keshab K. Parhi
    Reducing bus transition activity by limited weight coding with codeword slimming. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:13-16 [Conf]
  4. Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino
    Supporting system-level power exploration for DSP applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:17-22 [Conf]
  5. V. K. Pisini, Sofiène Tahar, Paul Curzon, Otmane Aït Mohamed, Xiaoyu Song
    Formal hardware verification by integrating HOL and MDG. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:23-28 [Conf]
  6. Salvador Mir, Benoît Charlot, Gabriela Nicolescu, P. Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz
    Towards design and validation of mixed-technology SOCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:29-33 [Conf]
  7. Jennifer L. White, Anthony S. Wojcik, Moon-Jung Chung, Travis E. Doom
    Candidate subcircuits for functional module identification in logic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:34-38 [Conf]
  8. Christoph Meinel, Christian Stangier
    Speeding up symbolic model checking by accelerating dynamic variable reordering. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:39-42 [Conf]
  9. Sandro Wefel, Paul Molitor
    Prove that a faulty multiplier is faulty!? [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:43-46 [Conf]
  10. Cheng-Kok Koh, Patrick H. Madden
    Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:47-52 [Conf]
  11. Sudhakar Bobba, Ibrahim N. Hajj
    High-performance bidirectional repeaters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:53-58 [Conf]
  12. Tom Chen, Alkan Cengiz
    Measuring routing congestion for multi-layer global routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:59-62 [Conf]
  13. Radu M. Secareanu, Eby G. Friedman
    Transparent repeaters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:63-66 [Conf]
  14. José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan
    A wave-pipelined router architecture using ternary associative memory. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:67-70 [Conf]
  15. Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
    A novel technique for sea of gates global routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:71-74 [Conf]
  16. David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
    On-chip inductance modeling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:75-80 [Conf]
  17. R. Venkatraman, Lalit M. Patnaik
    An evolutionary approach to timing driven FPGA placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:81-85 [Conf]
  18. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    Parallel algorithms for FPGA placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:86-94 [Conf]
  19. Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
    Fast and accurate estimation of floorplans in logic/high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:95-100 [Conf]
  20. George Gristede, Wei Hwang
    A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:101-106 [Conf]
  21. Hendrawan Soeleman, Kaushik Roy
    Digital CMOS logic operation in the sub-threshold region. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:107-112 [Conf]
  22. A. E. Hussein, Mohamed I. Elmasry
    Low power high speed analog-to-digital converter for wireless communications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:113-116 [Conf]
  23. Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin
    A comparative study of power efficient SRAM designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:117-122 [Conf]
  24. Virgil Andronache, Edwin Hsing-Mean Sha, Nelson L. Passos
    Design and analysis of efficient application-specific on-line page replacement techniques. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:123-128 [Conf]
  25. Helvio P. Peixoto, Margarida F. Jacome
    A new technique for estimating lower bounds on latency for high level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:129-132 [Conf]
  26. Bo-Sung Kim, Jun Dong Cho
    Maximizing memory data reuse for lower power motion estimation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:133-138 [Conf]
  27. Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Hu
    Efficient algorithms for acceptable design exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:139-142 [Conf]
  28. Qiao Li, Sung-Mo Kang
    Technology independent arbitrary device extractor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:143-146 [Conf]
  29. Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei
    Regression-based RTL power models for controllers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:147-152 [Conf]
  30. Bibhudatta Sahoo, Martin Kuhlmann, Keshab K. Parhi
    A low-power correlator. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:153-155 [Conf]
  31. Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu
    Behavioral-level partitioning for low power design in control-dominated application. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:156-161 [Conf]
  32. Hung-Jung Chen, Bradley S. Carlson
    Power estimation for a submicron CMOS inverter driving a CRC interconnect load. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:162-166 [Conf]
  33. Gary L. Dare, Charles A. Zukowski
    Accuracy management for mixed-mode digital VLSI simulation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:167-170 [Conf]
  34. Kevin T. Tang, Eby G. Friedman
    Noise estimation due to signal activity for capacitively coupled CMOS logic gates. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:171-176 [Conf]
  35. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    SPARTA: Simulation of Physics on a Real-Time Architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:177-182 [Conf]
  36. Qiao Li, Sung-Mo Kang
    Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:183-188 [Conf]
  37. Craig Beebe, Jo Dale Carothers, Alfonso Ortega
    MCM placement using a realistic thermal model. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:189-192 [Conf]
  38. Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
    A sensitivity based placer for standard cells. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:193-196 [Conf]
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