Conferences in DBLP

ACM Great Lakes Symposium on VLSI (glvlsi)
2001 (conf/glvlsi/2001)

1. Leila Barakatain, Sofiène Tahar, Jean Lamarche, Jean-Marc Gendreau
   Practical approaches to the verification of a telecom megacell using FormalCheck. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:1-6 [Conf]
   
2. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
   A novel reseeding technique for accumulator-based test pattern generation. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:7-12 [Conf]
   
3. Irith Pomeranz, Sudhakar M. Reddy
   ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:13-18 [Conf]
   
4. Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man
   Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:19-24 [Conf]
   
5. Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh
   Layout aware retiming. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:25-30 [Conf]
   
6. Zhong Wang, Edwin Hsing-Mean Sha, Yuke Wang
   Optimal partitioning and balanced scheduling with the maximal overlap of data footprints. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:31-36 [Conf]
   
7. Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
   SOI for asynchronous dynamic circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:37-42 [Conf]
   
8. Ram Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar
   Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:43-44 [Conf]
   
9. Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara
   Challenges in integrated CMOS transceivers for short distance wireless. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:45-50 [Conf]
   
10. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    An accurate evaluation of routing density for symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:51-55 [Conf]
    
11. Mehmet Can Yildiz, Patrick H. Madden
    Preferred direction Steiner trees. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:56-61 [Conf]
    
12. Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
    Faster and more accurate wiring evaluation in interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:62-67 [Conf]
    
13. Mehmet Can Yildiz, Patrick H. Madden
    Global objectives for standard cell placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:68-72 [Conf]
    
14. Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook
    A circuit level implementation of an adaptive issue queue for power-aware microprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:73-78 [Conf]
    
15. Bipul Das, Swapna Banerjee
    A CORDIC based array architecture for complex discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:79-84 [Conf]
    
16. José G. Delgado-Frias, Girish B. Ratanpal
    A VLSI wrapped wave front arbiter for crossbar switches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:85-88 [Conf]
    
17. Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang
    Effective algorithms for cache-level compression. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:89-92 [Conf]
    
18. Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
    2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:93-96 [Conf]
    
19. Malay K. Ganai, Adnan Aziz
    Rarity based guided state space search. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:97-102 [Conf]
    
20. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    Who are the alternative wires in your neighborhood? (alternative wires identification without search). [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:103-108 [Conf]
    
21. Yu-Min Lee, Charlie Chung-Ping Chen
    Hierarchical model order reduction for signal-integrity interconnect synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:109-114 [Conf]
    
22. Min Xu, Lei He
    An efficient model for frequency-dependent on-chip inductance. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:115-120 [Conf]
    
23. Lijun Gao, Keshab K. Parhi
    Models for power consumption and power grid noise due to datapath transition activity. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:121-126 [Conf]
    
24. Deepak Srivastava
    Electronic devices, structures and transport in carbon based materials: molecular electronics and quantum computing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:127- [Conf]
    
25. Mark C. Hersam
    Single molecule electronics. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:128- [Conf]
    
26. John P. Denton, Sang Woo Pae, Gerold W. Neudeck
    Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:129-132 [Conf]
    
27. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Transistor sizing for reliable domino logic design in dual threshold voltage technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:133-138 [Conf]
    
28. José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
    Practical low-cost CPL implementations threshold logic functions. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:139-144 [Conf]
    
29. A. P. Preethy, Damu Radhakrishnan, Amos Omondi
    A high performance RNS multiply-accumulate unit. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:145-148 [Conf]
    
30. Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
    A fast hybrid carry-lookahead/carry-select adder design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:149-152 [Conf]