Conferences in DBLP
Florentin Dartu , Anirudh Devgan , Noel Menezes Variability modeling and variability-aware design in deep submicron integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mikhail Popovich , Eby G. Friedman , Michael Sotman , Avinoam Kolodny On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. M. Vaseekar Kumar , Spyros Tragoudas Low power test generation for path delay faults using stability functions. [Citation Graph (0, 0)][DBLP ] Conf ] Noha Mahmoud , Maged Ghoneima , Yehea I. Ismail Physical limitations on the bit-rate of on-chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Vasilis F. Pavlidis , Eby G. Friedman Interconnect delay minimization through interlayer via placement in 3-D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Syed M. Alam , Donald E. Troxel , Carl V. Thompson Thermal aware cell-based full-chip electromigration reliability analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel A. Andersson , Lars J. Svensson , Per Larsson-Edefors Accounting for the skin effect during repeater insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Gerald G. Lopez , Giovanni Fiorenza , Thomas J. Bucelot , Phillip Restle , Mary Yvonne Lanzerotti Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Wang , Wenrui Gong , Ryan Kastner Instruction scheduling using MAX-MIN ant system optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Tay-Jyi Lin , Chie-Min Chao , Chia-Hsien Liu , Pi-Chen Hsiao , Shin-Kai Chen , Li-Chun Lin , Chih-Wei Liu , Chein-Wei Jen A unified processor architecture for RISC & VLIW DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Kimish Patel , Enrico Macii , Massimo Poncino Zero clustering: an approach to extend zero compression to instruction caches. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Hodjat , David Hwang , Bo-Cheng Lai , Kris Tiri , Ingrid Verbauwhede A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Shyamkumar Thoziyoor , Jay B. Brockman , Daniel Rinzler PIM lite: a multithreaded processor-in-memory prototype. [Citation Graph (0, 0)][DBLP ] Conf ] Tian Xia , Peilin Song , Hao Zheng Characterizing the VCO jitter due to the digital simultaneous switching noise. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Iizuka , Makoto Ikeda , Kunihiro Asada Exact minimum-width transistor placement without dual constraint for CMOS cells. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Suthar , Shantanu Dutt High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. [Citation Graph (0, 0)][DBLP ] Conf ] Xiren Wang , Wenjian Yu , Zeyi Wang , Xianlong Hong An improved direct boundary element method for substrate coupling resistance extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Generating decision regions in analog measurement spaces. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir Integer linear programming based energy optimization for banked DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Jain , David Blaauw Slack borrowing in flip-flop based sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene Goldberg On equivalence checking and logic synthesis of circuits with a common specification. [Citation Graph (0, 0)][DBLP ] Conf ] Rui Tang , Fengming Zhang , Yong-Bin Kim Quantum-dot cellular automata SPICE macro model. [Citation Graph (0, 0)][DBLP ] Conf ] Nirmal Ramalingam , Sanjukta Bhanja Causal probabilistic input dependency learning for switching model in VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Yan , Dilip V. Sarwate Area-efficient two-dimensional architectures for finite field inversion and division. [Citation Graph (0, 0)][DBLP ] Conf ] Jaehong Ko , Wookwan Lee , Soo-Won Kim 2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Fu , Shigetoshi Nakatake , Yasuhiro Takashima , Yoji Kajitani The oct-touched tile: a new architecture for shape-based routing. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Liu , Thanyapat Sakunkonchak , Satoshi Komatsu , Masahiro Fujita System level design language extensions for timed/untimed digital-analog combined system design. [Citation Graph (0, 0)][DBLP ] Conf ] Walid Elgharbawy , Pradeep Golconda , Magdy A. Bayoumi Noise-tolerant high fan-in dynamic CMOS circuit design. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Yang , Cherry Wakayama , C.-J. Richard Shi Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Hailong Yao , Yici Cai , Xianlong Hong , Qiang Zhou Improved multilevel routing with redundant via placement for yield and reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Qin , Tsutomu Sasao , Yukihiro Iguchi An FPGA design of AES encryption circuit with 128-bit keys. [Citation Graph (0, 0)][DBLP ] Conf ] Eun-Gu Jung , Jeong-Gun Lee , Sang-Hoon Kwak , Kyoung-Sun Jhang , Jeong-A. Lee , Dong-Soo Har High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Liu , Sheqin Dong , Xianlong Hong Fixed-outline floorplanning based on common subsequence. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihiro Uchida , Sadahiro Tani , Masanori Hashimoto , Shuji Tsukiyama , Isao Shirakawa Interconnect capacitance extraction for system LCD circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Yang , Zine-Eddine Abid , Wei Wang Two-prime RSA immune cryptosystem and its FPGA implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Sushanta K. Mandal , Arijit De , Amit Patra , Shamik Sural A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs. [Citation Graph (0, 0)][DBLP ] Conf ] Yulei Weng , Alex Doboli Digital cell macro-model with regular substrate template and EKV based MOSFET model. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu C. Vimjam , Manan Syal , Michael S. Hsiao Untestable fault identification through enhanced necessary value assignments. [Citation Graph (0, 0)][DBLP ] Conf ] Stelios Neophytou , Maria K. Michael , Spyros Tragoudas Test set enhancement for quality transition faults using function-based methods. [Citation Graph (0, 0)][DBLP ] Conf ] Hamidreza Hashempour , Fabrizio Lombardi Two dimensional reordering of functional test data for compression by ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Jiang Brandon Liu , Magdy S. Abadir , Andreas G. Veneris , Sean Safarpour Diagnosing multiple transition faults in the absence of timing information. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Cristina Marconcini , Graziano Pravadelli An EFSM-based approach for functional ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Vankamamidi , Marco Ottavi , Fabrizio Lombardi Tile-based design of a serial memory in QCA. [Citation Graph (0, 0)][DBLP ] Conf ] Kuan Zhou , John F. McDonald Multi-GHz SiGe design methodologies for reconfigurable computing. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Beckett Low-power circuits using dynamic threshold devices. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Stephen Smith , Sung Kyu Lim QCA channel routing with wire crossing minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Qinglang Luo , Xianlong Hong , Qiang Zhou , Yici Cai A new algorithm for layout of dark field alternating phase shifting masks. [Citation Graph (0, 0)][DBLP ] Conf ] Vida Ilderem Research and development for seamless mobility. [Citation Graph (0, 0)][DBLP ] Conf ] Sookyoung Kim , Thomas L. Martin DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systems. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Deng , Martin D. F. Wong Energy optimization in memory address bus structure for application-specific systems. [Citation Graph (0, 0)][DBLP ] Conf ] Somsubhra Mondal , Seda Ogrenci Memik Fine-grain leakage optimization in SRAM based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yuantao Peng , Xun Liu A sensitivity analysis of low-power repeater insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald P. Lajaunie , Michael S. Hsiao An effective and efficient ATPG-based combinational equivalence checker. [Citation Graph (0, 0)][DBLP ] Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Forward image computation with backtracing ATPG and incremental state-set construction. [Citation Graph (0, 0)][DBLP ] Conf ] Ghiath Al Sammane , Dominique Borrione , Remy Chevallier Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Sean Safarpour , Görschwin Fey , Andreas G. Veneris , Rolf Drechsler Utilizing don't care states in SAT-based bounded sequential problems. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir Energy management in software-controlled multi-level memory hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] Mirko Loghi , Martin Letis , Luca Benini , Massimo Poncino Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. [Citation Graph (0, 0)][DBLP ] Conf ] Gokhan Memik , Mahmut T. Kandemir , Arindam Mallik Load elimination for low-power embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Cheng Kuo , Yu-Chien Wang , Chien-Nan Jimmy Liu An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu Liu , Yang Song , Takeshi Ikenaga , Satoshi Goto A VLSI array processing oriented fast fourier transform algorithm and hardware implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Saleh , Mehrdad Najibi , Mohsen Naderi , Hossein Pedram , Mehdi Sedighi A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiano Forzan , Davide Pandini A complete methodology for an accurate static noise analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Felipe S. Marques , Renato P. Ribas , Sachin S. Sapatnekar , André Inácio Reis A new approach to the use of satisfiability in false path detection. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew R. Guthaus , Natesan Venkateswaran , Vladimir Zolotov , Dennis Sylvester , Richard B. Brown Optimization objectives and models of variation for statistical gate sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Shahin Nazarian , Massoud Pedram , Emre Tuncer An empirical study of crosstalk in VDSM technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Kuan Jen Lin , Shih Hao Huang , Shih Wen Chen A hardware/software codesign approach for programmable IO devices. [Citation Graph (0, 0)][DBLP ] Conf ] Srivathsan Krishnamohan , Nihar R. Mahapatra Analysis and design of soft-error hardened latches. [Citation Graph (0, 0)][DBLP ] Conf ] Hailin Jiang , Kai Wang , Malgorzata Marek-Sadowska Clock skew bounds estimation under power supply and process variations. [Citation Graph (0, 0)][DBLP ] Conf ] João Daniel Togni , Renato P. Ribas , Maria Lucia Blamck Lisboa , André Inácio Reis Tool integration using the web-services approach. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Yuan , Gang Qu , Ankur Srivastava VLSI CAD tool protection by birthmarking design solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Sankalp Kallakuri , Nattawut Thepayasuwan , Alex Doboli , Eugene A. Feinberg A continuous time markov decision process based on-chip buffer allocation methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Fijany , Farrokh Vatan , Mohammad Mojarradi , Nikzad Benny Toomarian , Benjamin J. Blalock , Kerem Akarvardar , Sorin Cristoloveanu , Pierre Gentil The G4 -FET: a universal and programmable logic gate. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir , Mary Jane Irwin Using data compression in an MPSoC architecture for improving performance. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Hu , Vishwani D. Agrawal Dual-transition glitch filtering in probabilistic waveform power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Abhishek Mitra , Marcello Lajolo , Kanishka Lahiri SOFTENIT: a methodology for boosting the software content of system-on-chip designs. [Citation Graph (0, 0)][DBLP ] Conf ] Pietro Babighian , Luca Benini , Alberto Macii , Enrico Macii Low-overhead state-retaining elements for low-leakage MTCMOS design. [Citation Graph (0, 0)][DBLP ] Conf ] Hamidreza Hashempour , Luca Schiano , Fabrizio Lombardi Enhancing error resilience for reliable compression of VLSI test data. [Citation Graph (0, 0)][DBLP ] Conf ] Prassanna Sithambaram , Alberto Macii , Enrico Macii Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Bai , Nam Sung Kim , Dennis Sylvester , Trevor N. Mudge Total leakage optimization strategies for multi-level caches. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Gulati , Erik Brunvand Design of a cell library for asynchronous microengines. [Citation Graph (0, 0)][DBLP ] Conf ] Amitava Bhaduri , Ranga Vemuri Moment-driven coupling-aware routing methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Grad , James E. Stine New algorithms for carry propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsik Kim , Parija Sule , Nazanin Mansouri Exploiting PSL standard assertions in a theorem-proving-based verification environment. [Citation Graph (0, 0)][DBLP ] Conf ] Junwei Zhou , Andrew Mason Increasing design space of the instruction queue with tag coding. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Bastani , Charles A. Zukowski Characterization of monotonic static CMOS gates in a 65nm technology. [Citation Graph (0, 0)][DBLP ] Conf ] Srivathsan Krishnamohan , Nihar R. Mahapatra An analysis of the robustness of CMOS delay elements. [Citation Graph (0, 0)][DBLP ] Conf ] Ann Gordon-Ross , Frank Vahid , Nikil Dutt A first look at the interplay of code reordering and configurable caches. [Citation Graph (0, 0)][DBLP ] Conf ] Abdallah Merhebi , Otmane Aït Mohamed FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks. [Citation Graph (0, 0)][DBLP ] Conf ] Soroush Abbaspour , Hanif Fatemi , Massoud Pedram VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. [Citation Graph (0, 0)][DBLP ] Conf ] Vikas Sharma , Chien-Liang Chen , Chung-Ping Chen 1-V 7-mW dual-band fast-locked frequency synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Srivathsan Krishnamohan , Nihar R. Mahapatra Increasing the energy efficiency of pipelined circuits via slack redistribution. [Citation Graph (0, 0)][DBLP ] Conf ] Bahar Jalali Farahani , Mohammed Ismail Adaptive digital techniques to suppress quantization noise of Sigma Delta analog to digital converters. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Joshi , Jeffrey A. Davis Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. [Citation Graph (0, 0)][DBLP ] Conf ] Balasubramanian Sethuraman , Prasun Bhattacharya , Jawad Khan , Ranga Vemuri LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob R. Minz , Sung Kyu Lim , Cheng-Kok Koh 3D module placement for congestion and power noise reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Himanshu Kaul , Dennis Sylvester A novel buffer circuit for energy efficient signaling in dual-VDD systems. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Cooke , Hamid Mahmoodi-Meimand , Qikai Chen , Kaushik Roy Energy recovery clocked dynamic logic. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen C. Terry , Mohommad M. Mojarradi , Benjamin J. Blalock , Jesse A. Richmond Adaptive gate biasing: a new solution for body-driven current mirrors. [Citation Graph (0, 0)][DBLP ] Conf ] Farshad Moradi , Hamid Mahmoodi-Meimand , Ali Peiravi A high speed and leakage-tolerant domino logic for high fan-in gates. [Citation Graph (0, 0)][DBLP ] Conf ] Anuradha Agarwal , Glenn Wolfe , Ranga Vemuri Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Qinghua Liu , Malgorzata Marek-Sadowska A congestion-driven placement framework with local congestion prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-Chiou Wu , Rung-Bin Lin Reticle floorplanning of flexible chips for multi-project wafers. [Citation Graph (0, 0)][DBLP ] Conf ] Qingzhou (Ben) Wang , Devang Jariwala , John Lillis A study of tighter lower bounds in LP relaxation based placement. [Citation Graph (0, 0)][DBLP ] Conf ] 