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ACM Great Lakes Symposium on VLSI (glvlsi)
2007 (conf/glvlsi/2007)

  1. Philippe Magarshack
    Design challenges in 45nm and below: DFM, low-power and design for reliability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:1- [Conf]
  2. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:2-7 [Conf]
  3. Chunyue Liu, Xiaolang Yan, Xing Qin
    An optimized linear skewing interleave scheme for on-chip multi-access memory systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:8-13 [Conf]
  4. Sangyeun Cho
    I-cache multi-banking and vertical interleaving. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:14-19 [Conf]
  5. Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto
    A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:20-24 [Conf]
  6. Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack
    NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:25-30 [Conf]
  7. Yanming Jia, Yici Cai, Xianlong Hong
    Dummy fill aware buffer insertion during routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:31-36 [Conf]
  8. Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas
    Probabilistic gate-level power estimation using a novel waveform set method. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:37-42 [Conf]
  9. Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
    Robust wiring networks for DfY considering timing constraints. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:43-48 [Conf]
  10. Bin Zhou, Yizheng Ye, Yong-sheng Wang
    Simultaneous reduction in test data volume and test time for TRC-reseeding. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:49-54 [Conf]
  11. Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio
    SEU mitigation for sram-based fpgas through dynamic partial reconfiguration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:55-60 [Conf]
  12. Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob Abraham
    Estimating path delay distribution considering coupling noise. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:61-66 [Conf]
  13. Soheil Aminzadeh, Saeed Safari
    Co-evolutionary high-level test synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:67-72 [Conf]
  14. Tarun Sairam, Wei Zhao, Yu Cao
    Optimizing finfet technology for high-speed and low-power design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:73-77 [Conf]
  15. Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti
    Analysis of data dependence of leakage current in CMOS cryptographic hardware. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:78-83 [Conf]
  16. Yan Zhang, Mircea R. Stan
    Temperature-aware circuit design using adaptive body biasing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:84-89 [Conf]
  17. Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos
    A buffered crossbar-based chip interconnection framework supporting quality of service. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:90-95 [Conf]
  18. Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
    Exact sat-based toffoli network synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:96-101 [Conf]
  19. Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod
    Combinational equivalence checking for threshold logic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:102-107 [Conf]
  20. Nadine Gergel-Hackett, Garrett S. Rose, Peter Paliwoda, Christina A. Hacker, Curt A. Richter
    On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:108-113 [Conf]
  21. Juan Núñez, José M. Quintana, Maria J. Avedillo
    Operation limits in RTD-based ternary quantizers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:114-119 [Conf]
  22. Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson
    Transition-activity aware design of reduction-stages for parallel multipliers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:120-125 [Conf]
  23. Chun-Mok Chung, Jihong Kim, Dohyung Kim
    Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:126-131 [Conf]
  24. Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley
    GALS SoC interconnect bus for wireless sensor network processor platforms. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:132-137 [Conf]
  25. A. Robinson, Jim D. Garside
    Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:138-143 [Conf]
  26. Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede
    Side-channel resistant system-level design flow for public-key cryptography. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:144-147 [Conf]
  27. R. G. Raghavendra, Bharadwaj Amrutur
    Area efficient loop filter design for charge pump phase locked loop. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:148-151 [Conf]
  28. Dariusz Kania
    A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:152-155 [Conf]
  29. Dan Li, Tingcun Wei, Wei Wu
    A novel charge recycler for TFT-LCD source driver IC. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:156-159 [Conf]
  30. Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga
    Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:160-163 [Conf]
  31. Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis
    Compiler assisted architectural exploration for coarse grained reconfigurable arrays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:164-167 [Conf]
  32. Linga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal
    Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:168-171 [Conf]
  33. Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi
    RT level reliability enhancement by constructing dynamic TMRS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:172-175 [Conf]
  34. Atabak Mahram, Mehrdad Najibi, Hossein Pedram
    An asynchronous fpga logic cell implementation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:176-179 [Conf]
  35. Maurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera, Giuseppe D'Angelo, Giorgio Pasquettaz
    Real-time implementation of a time-frequency analysis scheme. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:180-183 [Conf]
  36. Maurizio Martina, Guido Masera
    Flexible blocks for high throughput serially concatenated convolutional codes. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:184-187 [Conf]
  37. Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
    Novel architectures for efficient (m, n) parallel counters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:188-191 [Conf]
  38. Mustafa Altun, Hakan Kuntman
    High CMRR current mode operational amplifier with a novel class AB input stage. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:192-195 [Conf]
  39. Barbara Cerato, Guido Masera, Peter Nilsson
    Hardware architecture for matrix factorization in mimo receivers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:196-199 [Conf]
  40. C. Hess, M. Wenk, Andreas Burg, P. Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner
    Reduced-complexity mimo detector with close-to ml error rate performance. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:200-203 [Conf]
  41. Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani
    Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:204-207 [Conf]
  42. Drew C. Ness, Christian J. Hescott, David J. Lilja
    Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:208-211 [Conf]
  43. Osman Musa Abdulkarim, Maitham Shams
    A symmetric mos current-mode logic universal gate for high speed applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:212-215 [Conf]
  44. Brandon L. Dell, Jonathan F. Bolus, Travis N. Blalock
    An automated unique tagging system using CMOS process variation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:216-218 [Conf]
  45. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A design kit for a fully working shared memory multiprocessor on FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:219-222 [Conf]
  46. Karthikeyan Lingasubramanian, Sanjukta Bhanja
    Probabilistic maximum error modeling for unreliable logic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:223-226 [Conf]
  47. Riaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski
    Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:227-230 [Conf]
  48. Kimish Patel, Wonbok Lee, Massoud Pedram
    Active bank switching for temperature control of the register file in a microprocessor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:231-234 [Conf]
  49. Chanseok Hwang, Peng Rong, Massoud Pedram
    Sleep transistor distribution in row-based MTCMOS designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:235-240 [Conf]
  50. Luca Sterpone, Massimo Violante
    A new decompression system for the configuration process of SRAM-based FPGAS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:241-246 [Conf]
  51. Kambiz Rahimi
    Minimizing peak power in synchronous logic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:247-252 [Conf]
  52. Cosmin Popa
    Linearized CMOS active resistor independent on the bulk effect. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:253-256 [Conf]
  53. Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu (Jerry) Qi, Mircea R. Stan
    Structured and tuned array generation (STAG) for high-performance random logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:257-262 [Conf]
  54. Frank Sill, Jiaixi You, Dirk Timmermann
    Design of mixed gates for leakage reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:263-268 [Conf]
  55. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Modeling and estimating leakage current in series-parallel CMOS networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:269-274 [Conf]
  56. Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun
    Analyzing and modeling process balance for sub-threshold circuit design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:275-280 [Conf]
  57. Chih-Nan Wu, Wei-Chung Cheng
    Viewing direction-aware backlight scaling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:281-286 [Conf]
  58. Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
    Synthesis of irregular combinational functions with large don't care sets. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:287-292 [Conf]
  59. Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    DAG based library-free technology mapping. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:293-298 [Conf]
  60. Mehrdad Najibi, Kamran Saleh, Hossein Pedram
    Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:299-304 [Conf]
  61. Andrea Ricci, Ilaria De Munari, Paolo Ciampolini
    An evolutionary approach for standard-cell library reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:305-310 [Conf]
  62. Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias
    Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:311-316 [Conf]
  63. Sachin S. Sapatnekar
    Computer-aided design of 3d integrated circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:317- [Conf]
  64. Jamil Kawa, Charles Chiang
    DFM issues for 65nm and beyond. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:318-322 [Conf]
  65. Hai Lin, Yunsi Fei
    Utilizing custom registers in application-specific instruction set processors for register spills elimination. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:323-328 [Conf]
  66. Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi
    Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:329-334 [Conf]
  67. Alberto Dassatti, Simone Zezza, Mario Nicola, Guido Masera
    Beyond 3G wireless communication system prototype. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:335-340 [Conf]
  68. Luca Sterpone, Massimo Violante
    A new hardware architecture for performing the gridding of DNA microarray images. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:341-346 [Conf]
  69. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    A design methodology for space-time adapter. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:347-352 [Conf]
  70. Tarvo Raudvere, Ingo Sander, Axel Jantsch
    A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:353-358 [Conf]
  71. Amin Farmahini Farahani, Mehdi Kamal, Seid Mehdi Fakhraie, Saeed Safari
    HW/SW partitioning using discrete particle swarm. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:359-364 [Conf]
  72. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:365-370 [Conf]
  73. Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
    Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:371-376 [Conf]
  74. Roghoyeh Salmeh, Brent Maundy
    A 5 GHz wide band input and output matched low noise amplifier. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:377-380 [Conf]
  75. Himanshu Arora, Nikolaus Klemmer, Patrick Wolf
    A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:381-386 [Conf]
  76. Paolo Bernardi, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez
    Design of an UHF RFID transponder for secure authentication. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:387-392 [Conf]
  77. Fei He, Xiaoyu Song, Ming Gu, Jiaguang Sun
    Effective heuristics for counterexample-guided abstraction refinement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:393-398 [Conf]
  78. Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham
    Reducing verification overhead with RTL slicing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:399-404 [Conf]
  79. Ralf Wimmer, Marc Herbstritt, Bernd Becker
    Optimization techniques for BDD-based bisimulation computation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:405-410 [Conf]
  80. Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
    Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:411-416 [Conf]
  81. Anna Bernasconi, Valentina Ciriani, Roberto Cordone
    An approximation algorithm for fully testable kEP-SOP networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:417-422 [Conf]
  82. Orkun Saglamdemir, Ömer Yetik, Selçuk Talay, Günhan Dündar
    A coefficient optimization and architecture selection tool for SD modulators considering component non-idealities. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:423-428 [Conf]
  83. Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
    Hand-in-hand verification of high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:429-434 [Conf]
  84. Taeko Matsunaga, Yusuke Matsunaga
    Area minimization algorithm for parallel prefix adders under bitwise delay constraints. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:435-440 [Conf]
  85. Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A new algorithm for the largest compositionally progressive solution of synchronous language equations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:441-444 [Conf]
  86. Giovanni Agosta, Francesco Bruschi, Donatella Sciuto
    An efficient cost-based canonical form for Boolean matching. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:445-448 [Conf]
  87. Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson
    Evaluation of using active circuitry for substrate noise suppression. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:449-452 [Conf]
  88. Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
    The effect of temperature on cache size tuning for low energy embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:453-456 [Conf]
  89. Samuel Evain, Jean-Philippe Diguet
    Efficient space-time noc path allocation based on mutual exclusion and pre-reservation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:457-460 [Conf]
  90. Zhentao Yu, Marios C. Papaefthymiou, Xun Liu
    Skew spreading for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:461-464 [Conf]
  91. Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
    Block placement to ensure channel routability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:465-468 [Conf]
  92. Manuel Barros, Jorge Guilherme, Nuno Horta
    GA-SVM feasibility model and optimization kernel applied to analog IC design automation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:469-472 [Conf]
  93. Xinjie Wei, Yici Cai, Xianlong Hong
    Physical aware clock skew rescheduling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:473-476 [Conf]
  94. Rachit Kumar Gupta, Vikas Narang, H. M. Roopashree, Vinod Menezes
    A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:477-480 [Conf]
  95. Koji Ohashi, Mineo Kaneko
    Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:481-484 [Conf]
  96. Raffaella Gentilini, Klaus Schneider, Alexander Dreyer
    Three-valued automated reasoning on analog properties. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:485-488 [Conf]
  97. Olga Golubeva, Mirko Loghi, Massimo Poncino
    On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:489-492 [Conf]
  98. Daniel Große, Rüdiger Ebendt, Rolf Drechsler
    Improvements for constraint solving in the systemc verification library. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:493-496 [Conf]
  99. Hamed Aminzadeh, Mohammad Danaie
    Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:497-500 [Conf]
  100. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
  101. Marcello Mura, Marco Paolieri, Luca Negri, Mariagiovanna Sami
    StateCharts to systemc: a high level hardware simulation approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:505-508 [Conf]
  102. Marco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini
    A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:509-512 [Conf]
  103. Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
    Improvement of power distribution network using correlation-based regression analysis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:513-516 [Conf]
  104. Deniz Dal, Nazanin Mansouri
    A high-level register optimization technique for minimizing leakage and dynamic power. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:517-520 [Conf]
  105. Hamid Reza Kheirabadi, Morteza Saheb Zamani
    An efficient net ordering algorithm for buffer insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:521-524 [Conf]
  106. Jia Wang, Ming-Yang Kao, Hai Zhou
    Address generation for nanowire decoders. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:525-528 [Conf]
  107. Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
    Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:529-533 [Conf]
  108. Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
    Efficient pipelining for modular multiplication architectures in prime fields. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:534-539 [Conf]
  109. Chichyang Chen, Paul Chow
    Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:540-545 [Conf]
  110. Dong-Ho Lee, Jong-Soo Oh
    Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:546-551 [Conf]
  111. Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat
    Floorplan repair using dynamic whitespace management. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:552-557 [Conf]
  112. Ali Jahanian, Morteza Saheb Zamani
    Improved timing closure by early buffer planning in floor-placement design flow. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:558-563 [Conf]
  113. Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
    An effective buffer planning algorithm for IP based fixed-outline SOC placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:564-569 [Conf]
  114. Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
    New timing and routability driven placement algorithms for FPGA synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:570-575 [Conf]
  115. Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
    RT-level vector selection for realistic peak power simulation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:576-581 [Conf]
  116. Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
    A fast clock scheduling for peak power reduction in LSI. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:582-587 [Conf]
  117. Prashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay
    A path based modeling approach for dynamic power estimation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:588-593 [Conf]
  118. Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung
    Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:594-599 [Conf]
  119. Georges G. E. Gielen
    Future trends for wireless communication frontends in nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:600-605 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002