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Conferences in DBLP

Hawaii International Conference on System Sciences (HICSS) (hicss)
1994 (conf/hicss/1994-1)

  1. L. Ridgway Scott
    Computer Design: A New Grand Challenge: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:3-6 [Conf]
  2. R. Kent Smith, William M. Coughran Jr.
    Computational Challenges in Simulations of ULSI Semiconductor Devices. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:7-15 [Conf]
  3. Yegnashankar Parasuram, Edward P. Stabler, Shiu-Kai Chin
    Parallel implementation of BDD Algorithms using a Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:16-25 [Conf]
  4. Brad L. Hutchings, Tony M. Carter
    High-Speed Circuit Design: CAD Tools and Computational Challenges. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:26-35 [Conf]
  5. Aurobindo Dasgupta, Israel Koren
    An Algorithm for Area and Delay Optimization of Sequential Machines through Decomposition. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:36-45 [Conf]
  6. Babak Bagheri, Andrew Ilin, L. Ridgway Scott
    Parallel 3-D MOSFET Simulation. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:46-55 [Conf]
  7. Jordi Cortadella, José A. B. Fortes, Edward A. Lee
    Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:56-57 [Conf]
  8. Wayne Burleson
    Using Regular Array Methods for DSP Module Synthesis. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:58-67 [Conf]
  9. Guoning Liao, Erik R. Altman, Vinod K. Agarwal, Guang R. Gao
    A Comparative Study of Multiprocessor List Scheduling Heuristics. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:68-77 [Conf]
  10. Hans-Jürgen Herpel, Michael Held, Manfred Glesner
    A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:78-86 [Conf]
  11. William Cammack, Mark Paley
    Fixpt: A C++ Method for Development of Fixed Point Digital Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:87-95 [Conf]
  12. Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:96-104 [Conf]
  13. Joël Champeau, Luc Le Pape, Bernard Pottier, Stéphane Rubini, Eric Gautrin, Laurent Perraudeau
    Flexible Parallel FPGA-Based Architectures with ArMe. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:105-113 [Conf]
  14. Vijay K. Jain, Hiroomi Hikawa
    Parallel Architecture for Universal Digital Signal Processing. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:114-123 [Conf]
  15. Catherine H. Gebotys, Robert J. Gebotys
    Application-Specific Architectures for Field-Programmable VLSI Technologies. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:124-131 [Conf]
  16. Wen-Hann Wang, Shreekant S. Thakkar
    Enabling Multiprocessor Technology: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:132-133 [Conf]
  17. Mike Galles, Eric Williams
    Performance Optimizations, Implementation, and Verification of the SGI Challenge Multiprocessor. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:134-143 [Conf]
  18. Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, David Lee, Michael Parkin
    The S3mp Scalable Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:144-153 [Conf]
  19. Stein Gjessing, Glen Stone
    Performance of the RamLink Memory Architecture. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:154-162 [Conf]
  20. Richard N. Zucker, Jean-Loup Baer
    Software versus Hardware Coherence: Performance versus Cos. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:163-172 [Conf]
  21. Ziqiang Liu, José Duato
    Adaptive Unicast and Multicast in 3D Mesh Networks. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:173-183 [Conf]
  22. Thomas M. Conte, Charles E. Gimarc
    Fast Simulation of Computer Architectures: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:184- [Conf]
  23. H. A. Rizvi, James B. Sinclair, J. Robert Jump, J. Carson
    Execution-Driven Simulation of a Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:185-194 [Conf]
  24. Wayne Yamamoto, Mauricio J. Serrano, Adam R. Talcott, Roger C. Wood, Mario Nemirovsky
    Performance Estimation of Multistreamed, Supersealar Processors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:195-204 [Conf]
  25. Gary Lauterbach
    Accelerating Architectural Simulation by Parallel Execution of Trace Samples. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:205-210 [Conf]
  26. John W. C. Fu, Janak H. Patel
    Trace Driven Simulation using Sampled Traces. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:211-220 [Conf]
  27. Si-En Chang, Chia-Chang Hsu
    Efficient Simulation Methods for Multi-Level Cache Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:221-230 [Conf]
  28. Santosh G. Abraham, Rabin A. Sugumar
    Fast Efficient Simulation of Write-Buffer Configurations. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:231-240 [Conf]
  29. Gudjon Hermannsson, Ai Li, Larry D. Wittie
    EC/DSIM: A Frontend and Simulator for Huge Parallel Systems. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:241-250 [Conf]
  30. Bob Boothe
    Fast Accurate Simulation of Large Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:251-260 [Conf]
  31. Alexander R. Robertson, Roland N. Ibbett
    HASE: A Flexible High Performance Architecture Simulator. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:261-270 [Conf]
  32. Sathiamoorthy Manoharan, Nigel P. Topham, A. W. R. Crawford
    Trace-Driven Simulation of Decoupled Architectures. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:271-279 [Conf]
  33. Vojin G. Oklobdzija
    High-Performance Computer Arithmetic and Implementations: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:280-281 [Conf]
  34. Yousuke Ohno, Junichiro Makino, Izumi Hachisu, Toshikazu Ebisuzaki, Daiichiro Sugimoto
    DREAM-1A: Special-Purpose Computer for Computational Fluid Dynamics. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:282-291 [Conf]
  35. Eiichiro Kokubo, Junichiro Makino, Makoto Taiji
    HARP-1: A Special-Purpose Computer for itN-body Simulation with the Hermite Integrator. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:292-301 [Conf]
  36. Makino Taiji, Junichiro Makino, Eiichiro Kokubo, Toshikazu Ebisuzaki, Daiichiro Sugimoto
    HARP Chip: A.600 Mflops Application-Specific LSI for Astrophysical itN-body Simulations. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:302-311 [Conf]
  37. Andrej Skorc, Veljko M. Milutinovic
    Architectural Requirements for Multimedia Image Compression, and a Solution Based on VLSI Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:312-320 [Conf]
  38. Alberto Broggi
    Speeding-up Mathematical Morphology Computations with Special-Purpose Array Processors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:321-330 [Conf]
  39. Paolo Montuschi, Luigi Ciminiera
    Radix-2 Division with Quotient Digit Prediction without Prescaling. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:331-338 [Conf]
  40. Jack Bukkoldt Andersen, Anders Fargemand Nielsen, Ole Olsen
    A Systolic ON-LINE Non-Restoring Division Scheme. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:339-348 [Conf]
  41. W. F. Wong, Eiichi Goto
    Fast Evaluation of the Elementary Functions in Double Precision. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:349-359 [Conf]
  42. Pohua P. Chang
    Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:360- [Conf]
  43. Pradeep K. Dubey, Arvind Krishna, Michael J. Flynn
    Analytical Modeling of Multithreaded Pipeline Performance. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:361-367 [Conf]
  44. Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
    Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:368-377 [Conf]
  45. Phenil Patadia, Vijay Karani, Krishna M. Kavi, Ponnarasu Shanmugam, Behrooz Shirazi, Ali R. Hurson
    Improvements to the ETS Dynamic Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:378-387 [Conf]
  46. Feipei Lai, Fong-chou Tsai
    A Pipeline Bubbles Reduction Technique for the Monsoon Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:388-397 [Conf]
  47. Takaya Arita, Hiromitsu Takagi, Masahiro Sowa
    V++: An Instruction-Restructurable Processor Architecture. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:398-408 [Conf]
  48. John W. C. Fu, A. L. Narasimha Reddy
    Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:409-411 [Conf]
  49. Dimitrios Stiliadis, Anujan Varma
    Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:412-421 [Conf]
  50. Ju-Ho Tang, Kimming So
    Performance and Design Choices of Level-Two Caches. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:422-430 [Conf]
  51. Sally A. McKee, Robert H. Klenke, Andrew J. Schwab, William A. Wulf, Steven A. Moyer, James H. Aylor, Charles Y. Hitchcock
    Experimental Implementation of Dynamic Access Ordering. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:431-440 [Conf]
  52. Arnold J. Niessen, Harry A. G. Wijshoff
    Memory Hardware Support for Sparse Computations. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:441-450 [Conf]
  53. Brian Marsh, Fred Douglis, P. Krishnan
    Flash Memory File Caching for Mobile Computers. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:451-461 [Conf]
  54. Aruna V. Ramanan, Harry F. Jordan, Jon R. Sauer, Daniel J. Blumenthal
    An Extended Fiber-Optic Backplane for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:462-470 [Conf]
  55. Francis Reichmeyer, Salim Hariri, Wang Song, Kamal Jabbour
    An Optical Hypercube Local Area Network. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:471-480 [Conf]
  56. Pawel Gburzynski, Jacek Maitan, D. Robertson
    A Simple and Scalable Architecture for Rapidly Expandable Networks. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:481-490 [Conf]
  57. Aloke Guha
    Optical Packet Switching Architectures for Distributed Computing. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:491-498 [Conf]
  58. Michael S. Borella, Biswanath Mukherjee, Feiling Jia, S. Ramamurthy, Dhritiman Banerjee, Jason Iness
    Optical Interconnects for Multiprocessor Architectures Using Wavelength-Division Multiplexing. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:499-508 [Conf]
  59. Paul R. Prucnal
    Time-Division Optical Micro-Area Networks. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:509-519 [Conf]
  60. Per Stenström
    Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:520-521 [Conf]
  61. Erik Hagersten, Ashley Saulsbury, Anders Landin
    Simple COMA Node Implementations. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:522-533 [Conf]
  62. David Glasco, Bruce Delagi, Michael J. Flynn
    Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:534-545 [Conf]
  63. Manu Thapar
    Interleaved Dual Tag Directory Scheme for Cache Coherence. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:546-553 [Conf]
  64. Patricia J. Teller, Allan Gottlieb
    Locating Multiprocessor TLBs at Memory. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:554-563 [Conf]
  65. Susan Flynn Hummel
    Adding Fault-Tolerance to Algorithms for Weak Consistence. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:564-573 [Conf]
  66. Gudjon Hermannsson, Larry D. Wittie
    Fast Locks in Distributed Shared Memory Systems. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:574-583 [Conf]
  67. David K. Probst
    Programming, Compiling and Executing Partially-Ordered Instruction Streams on Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:584-593 [Conf]
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