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Conferences in DBLP
- K. Y. Wu, P. K. H. Ng, Xing Dong Jia, Richard M. M. Chen, A. M. Layfield
Performance tuning of a multiprocessor sparse matrix equation solver. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:4-13 [Conf]
- Ireneusz Karkowski
Architectural synthesis with possibilistic programming. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:14-22 [Conf]
- Glenn Jennings
Symbolic incompletely specified functions for correct evaluation in the presence of indeterminate input values. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:23-31 [Conf]
- Dejan Raskovic, Emil Jovanov, Aleksandar Janicijevic, Veljko M. Milutinovic
An implementation of hash based ATM router chip. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:32-40 [Conf]
- Catherine H. Gebotys, Robert J. Gebotys
Optimized mapping of video applications to hardware-software for VLSI architectures. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:41-48 [Conf]
- Oleg A. Panfilov
Performance analysis of RAID-5 disk arrays. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:49-60 [Conf]
- Kuei Yu Wang, Dan C. Marinescu
Correlation of the paging activity of individual node programs in the SPMD execution mode. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:61-0 [Conf]
- Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic
A survey of distributed shared memory systems. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:74-84 [Conf]
- Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde
Reflective-memory multiprocessor. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:85-94 [Conf]
- Mark Natale, Mark Baker, Roger Collins, David Wilson, Stephen Lucci, Izidor Gertner
Pentium MPP for OLTP applications. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:95-102 [Conf]
- Nicos Vekiarides
Fault-tolerant disk storage and file systems using reflective memory. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:103-113 [Conf]
- Mark Russinovich, Zary Segall
Application-transparent checkpointing in Mach 3.O/UX. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:114-123 [Conf]
- Greg Schaffer
MPP UNIX enhancements for OLTP applications. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:124-133 [Conf]
- Mark Aldred, Ilya Gertner, Stephen McKellar
A distributed lock manager on fault tolerant MPP . [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:134-136 [Conf]
- Gilberto Arnaiz
Tuning Oracle7 for nCUBE. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:137-139 [Conf]
- Milan Jovanovic, Milo Tomasevic, Veljko M. Milutinovic
A simulation-based comparison of two reflective memory approaches. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:140-0 [Conf]
Instruction Level Parallelism. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:151-152 [Conf]
- Siamak Arya, Howard Sachs, Sreeram Duvvuru
An architecture for high instruction level parallelism. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:153-162 [Conf]
- John G. Cleary, Murray Pearson, Husam Kinawi
The architecture of an optimistic CPU: the WarpEngine. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:163-172 [Conf]
- Sreeram Duvvuru, Siamak Arya
Evaluation of a branch target address cache. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:173-180 [Conf]
- Thomas Scholz, Michael Schäfers
An improved dynamic register array concept for high-performance RISC processors. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:181-190 [Conf]
- Marc Tremblay, Bill Joy, Ken Shin
A three dimensional register file for superscalar processors. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:191-201 [Conf]
- Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau
Reducing memory latency using a small software driven array cache. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:202-210 [Conf]
- Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu
A study of the effects of compiler-controlled speculation on instruction and data caches. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:211-220 [Conf]
- J. Stan Cox, David P. Howell, Thomas M. Conte
Commercializing profile-driven optimization. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:221-228 [Conf]
- Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
A comparative evaluation of software techniques to hide memory latency. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:229- [Conf]
Introduction. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:240-241 [Conf]
- Mårten Björkman, Fredrik Dahlgren, Per Stenström
Using hints to reduce the read miss penalty for flat COMA protocols. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:242-251 [Conf]
- Ian Watson, Alasdair Rawsthorne
Decoupled pre-fetching for distributed shared memory. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:252-261 [Conf]
- Alexandre E. Eichenberger, Santosh G. Abraham
Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:262-271 [Conf]
- Igor Tartalja, Veljko M. Milutinovic
A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:272-0 [Conf]
- Thomas D. Burd, Robert W. Brodersen
Energy efficient CMOS microprocessor design. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:288-297 [Conf]
- John Bunda, Donald S. Fussell, William C. Athas
Energy-efficient instruction set architecture for CMOS microprocessors. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:298-305 [Conf]
- Ching-Long Su, Alvin M. Despain
Cache designs for energy efficiency. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:306-315 [Conf]
- Priyadarsan Patra, Donald S. Fussell
Power-efficient delay-insensitive codes for data transmission. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:316-323 [Conf]
- Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye
A technique to determine power-efficient, high-performance superscalar processors. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1995, pp:324-333 [Conf]
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