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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
1997 (conf/hpca/1997)

  1. Liuxi Yang, Josep Torrellas
    Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:4-13 [Conf]
  2. Fredrik Dahlgren, Anders Landin
    Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:14-23 [Conf]
  3. Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. Tavares Fernandes
    Datapath Design for a VLIW Video Signal Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:24-0 [Conf]
  4. Xin Yuan, Rami G. Melhem, Rajiv Gupta
    Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:38-47 [Conf]
  5. Ram Kesavan, Kiran Bondalapati, Dhabaleswar K. Panda
    Multicast on Irregular Switch-Based Networks with Wormhole Routing. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:48-57 [Conf]
  6. Govindan Ravindran, Michael Stumm
    A Performance Comparison of Hierarchical Ring- and Mesh-Connected Multiprocessor Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:58-0 [Conf]
  7. Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve
    The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:72-83 [Conf]
  8. David I. August, Daniel A. Connors, John C. Gyllenhaal, Wen-mei W. Hwu
    Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:84-93 [Conf]
  9. Steven Wallace, Nader Bagherzadeh
    Multiple Branch and Block Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:94-0 [Conf]
  10. Kai Hwang, Choming Wang, Cho-Li Wang
    Evaluating MPI Collective Communication on the SP2, T3D, and Paragon Multicomputers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:106-115 [Conf]
  11. Beng-Hong Lim, Philip Heidelberger, Pratap Pattnaik, Marc Snir
    Message Proxies for Efficient, Protected Communication on SMP Clusters. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:116-127 [Conf]
  12. Babak Falsafi, David A. Wood
    Scheduling Communication on a SMP Node Parallel Machine. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:128-0 [Conf]
  13. Kevin Skadron, Douglas W. Clark
    Design Issues and Tradeoffs for Write Buffers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:144-155 [Conf]
  14. Bruce L. Jacob, Trevor N. Mudge
    Software-Managed Address Translation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:156-167 [Conf]
  15. Thomas Stricker, Thomas R. Gross
    Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:168-0 [Conf]
  16. Xiaohan Qin, Jean-Loup Baer
    On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:182-193 [Conf]
  17. Anand Sivasubramaniam
    Reducing the Communication Overhead of Dynamic Applications on Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:194-203 [Conf]
  18. Hazim Abdel-Shafi, Jonathan Hall, Sarita V. Adve, Vikram S. Adve
    An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:204-0 [Conf]
  19. Quinn Jacobson, Steve Bennett, Nikhil Sharma, James E. Smith
    Control Flow Speculation in Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:218-229 [Conf]
  20. Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller
    Advances of the Counterflow Pipeline Microarchitecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:230-236 [Conf]
  21. Roger Espasa, Mateo Valero
    Multithreaded Vector Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:237-0 [Conf]
  22. Pedro Trancoso, Josep-Lluis Larriba-Pey, Zheng Zhang, Josep Torrellas
    The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:250-260 [Conf]
  23. Cristiana Amza, Alan L. Cox, Sandhya Dwarkadas, Willy Zwaenepoel
    Software DSM Protocols that Adapt between Single Writer and Multiple Writer. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:261-271 [Conf]
  24. Zheng Zhang, Josep Torrellas
    Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:272-0 [Conf]
  25. Dileep Bhandarkar, Jason Ding
    Performance Characterization of the Pentium(r) Pro Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:288-299 [Conf]
  26. Derek B. Noonburg, John Paul Shen
    A Framework for Statistical Modeling of Superscalar Processor Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:298-309 [Conf]
  27. Sucheta Chodnekar, Viji Srinivasan, Aniruddha S. Vaidya, Anand Sivasubramaniam, Chita R. Das
    Towards a Communication Characterization Methodology for Parallel Applications. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:310-0 [Conf]
  28. Evangelos P. Markatos, Manolis Katevenis
    User-Level DMA without Operating System Kernel Modification. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:322-331 [Conf]
  29. Matt Welsh, Anindya Basu, Thorsten von Eicken
    ATM and Fast Ethernet Network Interfaces for User-Level Communication. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:332-342 [Conf]
  30. Binh Vien Dao, Sudhakar Yalamanchili, José Duato
    Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:343-352 [Conf]
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