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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
2004 (conf/hpca/2004)

  1. Victor Wen, Mark Whitney, Yatish Patel, John Kubiatowicz
    Exploiting Prediction to Reduce Power on Buses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:2-13 [Conf]
  2. Jian Li, José F. Martínez, Michael C. Huang
    The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:14-23 [Conf]
  3. Chris Gniady, Y. Charlie Hu, Yung-Hsiang Lu
    Program Counter Based Techniques for Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:24-35 [Conf]
  4. Russ Joseph, Zhigang Hu, Margaret Martonosi
    Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:36-47 [Conf]
  5. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Out-of-Order Commit Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:48-59 [Conf]
  6. Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally
    Stream Register Files with Indexed Access. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:60-72 [Conf]
  7. Jaume Abella, Antonio González
    Low-Complexity Distributed Issue Queue. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:73-83 [Conf]
  8. Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
    Hardware Support for Prescient Instruction Prefetch. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:84-95 [Conf]
  9. Kyle J. Nesbit, James E. Smith
    Data Cache Prefetching Using a Global History Buffer. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:96-105 [Conf]
  10. Spiros Kalogeropulos, Mahadevan Rajagopalan, Vikram Rao, Yonghong Song, Partha Tirumalai
    Processor Aware Anticipatory Prefetching in Loops. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:106-117 [Conf]
  11. Qingbo Zhu, Francis M. David, Christo F. Devaraj, Zhenmin Li, Yuanyuan Zhou, Pei Cao
    Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:118-129 [Conf]
  12. Enrique V. Carrera, Ricardo Bianchini
    Improving Disk Throughput in Data-Intensive Servers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:130-141 [Conf]
  13. Jianyong Zhang, Anand Sivasubramaniam, Hubertus Franke, Natarajan Gautam, Yanyong Zhang, Shailabh Nagar
    Synthesizing Representative I/O Workloads for TPC-H. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:142-151 [Conf]
  14. Srihari Makineni, Ravi R. Iyer
    Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:152-163 [Conf]
  15. Lu Peng, Jih-Kwon Peir, Konrad Lai
    Signature Buffer: Bridging Performance Gap between Registers and Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:164-175 [Conf]
  16. Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir
    Organizing the Last Line of Defense before Hitting the Memory Wall for CMP. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:176-185 [Conf]
  17. Pierre Michaud
    Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:186-197 [Conf]
  18. Ilhyun Kim, Mikko H. Lipasti
    Understanding Scheduling Replay Schemes. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:198-209 [Conf]
  19. Satish Narayanasamy, Yuanfang Hu, Suleyman Sair, Brad Calder
    Creating Converged Trace Schedules Using String Matching. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:210-221 [Conf]
  20. Todd E. Ehrhart, Sanjay J. Patel
    Reducing the Scheduling Critical Cycle Using Wakeup Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:222-231 [Conf]
  21. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring Wakeup-Free Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:232-243 [Conf]
  22. Ayose Falcón, Alex Ramírez, Mateo Valero
    A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:244-253 [Conf]
  23. Amit Gandhi, Haitham Akkary, Srikanth T. Srinivasan
    Reducing Branch Misprediction Penalty via Selective Branch Recovery. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:254-264 [Conf]
  24. Haitham Akkary, Srikanth T. Srinivasan, Rajendar Koltur, Yogesh Patil, Wael Refaai
    Perceptron-Based Branch Confidence Estimation. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:265-275 [Conf]
  25. Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos
    Accurate and Complexity-Effective Spatial Pattern Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:276-287 [Conf]
  26. Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin Lee
    Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:288-299 [Conf]
  27. Manel Fernández, Roger Espasa
    Link-Time Path-Sensitive Memory Redundancy Elimination. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:300-310 [Conf]
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