Conferences in DBLP
Victor Wen , Mark Whitney , Yatish Patel , John Kubiatowicz Exploiting Prediction to Reduce Power on Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Li , José F. Martínez , Michael C. Huang The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Gniady , Y. Charlie Hu , Yung-Hsiang Lu Program Counter Based Techniques for Dynamic Power Management. [Citation Graph (0, 0)][DBLP ] Conf ] Russ Joseph , Zhigang Hu , Margaret Martonosi Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Adrián Cristal , Daniel Ortega , Josep Llosa , Mateo Valero Out-of-Order Commit Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nuwan Jayasena , Mattan Erez , Jung Ho Ahn , William J. Dally Stream Register Files with Indexed Access. [Citation Graph (0, 0)][DBLP ] Conf ] Jaume Abella , Antonio González Low-Complexity Distributed Issue Queue. [Citation Graph (0, 0)][DBLP ] Conf ] Tor M. Aamodt , Paul Chow , Per Hammarlund , Hong Wang , John Paul Shen Hardware Support for Prescient Instruction Prefetch. [Citation Graph (0, 0)][DBLP ] Conf ] Kyle J. Nesbit , James E. Smith Data Cache Prefetching Using a Global History Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Spiros Kalogeropulos , Mahadevan Rajagopalan , Vikram Rao , Yonghong Song , Partha Tirumalai Processor Aware Anticipatory Prefetching in Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Qingbo Zhu , Francis M. David , Christo F. Devaraj , Zhenmin Li , Yuanyuan Zhou , Pei Cao Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management. [Citation Graph (0, 0)][DBLP ] Conf ] Enrique V. Carrera , Ricardo Bianchini Improving Disk Throughput in Data-Intensive Servers. [Citation Graph (0, 0)][DBLP ] Conf ] Jianyong Zhang , Anand Sivasubramaniam , Hubertus Franke , Natarajan Gautam , Yanyong Zhang , Shailabh Nagar Synthesizing Representative I/O Workloads for TPC-H. [Citation Graph (0, 0)][DBLP ] Conf ] Srihari Makineni , Ravi R. Iyer Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Lu Peng , Jih-Kwon Peir , Konrad Lai Signature Buffer: Bridging Performance Gap between Registers and Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Liu , Anand Sivasubramaniam , Mahmut T. Kandemir Organizing the Last Line of Defense before Hitting the Memory Wall for CMP. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Michaud Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration. [Citation Graph (0, 0)][DBLP ] Conf ] Ilhyun Kim , Mikko H. Lipasti Understanding Scheduling Replay Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Satish Narayanasamy , Yuanfang Hu , Suleyman Sair , Brad Calder Creating Converged Trace Schedules Using String Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Todd E. Ehrhart , Sanjay J. Patel Reducing the Scheduling Critical Cycle Using Wakeup Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Jie S. Hu , Narayanan Vijaykrishnan , Mary Jane Irwin Exploring Wakeup-Free Instruction Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Ayose Falcón , Alex Ramírez , Mateo Valero A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Gandhi , Haitham Akkary , Srikanth T. Srinivasan Reducing Branch Misprediction Penalty via Selective Branch Recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Haitham Akkary , Srikanth T. Srinivasan , Rajendar Koltur , Yogesh Patil , Wael Refaai Perceptron-Based Branch Confidence Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Chi F. Chen , Se-Hyun Yang , Babak Falsafi , Andreas Moshovos Accurate and Complexity-Effective Spatial Pattern Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Mazen Kharbutli , Keith Irwin , Yan Solihin , Jaejin Lee Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. [Citation Graph (0, 0)][DBLP ] Conf ] Manel Fernández , Roger Espasa Link-Time Path-Sensitive Memory Redundancy Elimination. [Citation Graph (0, 0)][DBLP ] Conf ] 