The SCEAS System
Navigation Menu

Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
1999 (conf/hpca/1999)

  1. Tarun Nakra, Rajiv Gupta, Mary Lou Soffa
    Global Context-Based Value Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:4-12 [Conf]
  2. David Brooks, Margaret Martonosi
    Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:13-22 [Conf]
  3. Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
    Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:23-32 [Conf]
  4. Kang Su Gatlin, Larry Carter
    Memory Hierarchy Considerations for Fast Transpose and Bit-Reversals. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:33-0 [Conf]
  5. Steven Wallace, Dean M. Tullsen, Brad Calder
    Instruction Recycling on a Multiple-Path Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:44-53 [Conf]
  6. Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy
    Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:54-58 [Conf]
  7. Joan-Manuel Parcerisa, Antonio González
    The Synergy of Multithreading and Access/Execute Decoupling. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:59-63 [Conf]
  8. Sébastien Hily, André Seznec
    Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:64-0 [Conf]
  9. John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Terry Tateyama
    Impulse: Building a Smarter Memory Controller. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:70-79 [Conf]
  10. Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf
    Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:80-89 [Conf]
  11. Kiyofumi Tanaka, Takashi Matsumoto, Kei Hiraki
    Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:90-0 [Conf]
  12. Jian Huang, David J. Lilja
    Exploiting Basic Block Value Locality with Block Reuse. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:106-114 [Conf]
  13. Eric Rotenberg, Quinn Jacobson, James E. Smith
    A Study of Control Independence in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:115-124 [Conf]
  14. Quinn Jacobson, James E. Smith
    Instruction Pre-Processing in Trace Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:125-129 [Conf]
  15. Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
    Distributed Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:130-134 [Conf]
  16. Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
    Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:135-0 [Conf]
  17. Maged M. Michael, Ashwini K. Nanda
    Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:142-151 [Conf]
  18. Ravi R. Iyer, Laxmi N. Bhuyan
    Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:152-160 [Conf]
  19. Stefanos Kaxiras, James R. Goodman
    Improving CC-NUMA Performance Using Instruction-Based Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:161-0 [Conf]
  20. Erik Hagersten, Michael Koster
    WildFire: A Scalable Path for SMPs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:172-181 [Conf]
  21. Babak Falsafi, David A. Wood
    Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:182-192 [Conf]
  22. Angelos Bilas, Dongming Jiang, Yuanyuan Zhou, Jaswinder Pal Singh
    Limits to the Performance of Software Shared Memory: A Layered Approach. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:193-0 [Conf]
  23. Yiming Hu, Qing Yang, Tycho Nightingale
    RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:204-213 [Conf]
  24. Thomas J. E. Schwarz, Jesse Steinberg, Walter A. Burkhard
    Permutation Development Data Layout (PDDL). [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:214-217 [Conf]
  25. Koji Inoue, Koji Kai, Kazuaki Murakami
    Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:218-222 [Conf]
  26. Yunseok Rhee, Joonwon Lee
    A Scalable Cache Coherent Scheme Exploiting Wormhole Routing Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:223-0 [Conf]
  27. Marius Pirvu, Laxmi N. Bhuyan, Nan Ni
    The Impact of Link Arbitration on Switch Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:228-235 [Conf]
  28. Aniruddha S. Vaidya, Anand Sivasubramaniam, Chita R. Das
    LAPSES: A Recipe for High Performance Adaptive Router Design. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:236-243 [Conf]
  29. Aske Plaat, Henri E. Bal, Rutger F. H. Hofman
    Sensitivity of Parallel Applications to Large Differences in Bandwidth and Latency in Two-Layer Interconnects. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:244-0 [Conf]
  30. Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas I. Kontothanassis, Daniel J. Scales, Michael L. Scott, Robert Stets
    Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:260-269 [Conf]
  31. Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin
    Using Lamport Clocks to Reason about Relaxed Memory Models. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:270-278 [Conf]
  32. Alan L. Cox, Eyal de Lara, Y. Charlie Hu, Willy Zwaenepoel
    A Performance Comparison of Homeless and Home-Based Lazy Release Consistency Protocols in Software Shared Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:279-283 [Conf]
  33. Chen-Chi Kuo, John B. Carter, Ravindra Kuramkote
    MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:284-0 [Conf]
  34. Yuanyuan Yang, Jianchao Wang
    Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:290-299 [Conf]
  35. José Duato, Sudhakar Yalamanchili, Blanca Caminero, Damon S. Love, Francisco J. Quiles
    MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:300-309 [Conf]
  36. Andrew Sohn, Yunheung Paek, Jui-Yuan Ku, Yuetsu Kodama, Yoshinori Yamaguchi
    Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:310-314 [Conf]
  37. Juan Miguel Martínez, Pedro López, José Duato
    Impact of Buffer Size on the Efficiency of Deadlock Detection. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:315-0 [Conf]
  38. David R. Kaeli, Bruce Jacobs
    Fifth Annual Workshop on Computer Education. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:320- [Conf]
  39. Anand Sivasubramaniam, Mario Lauria
    Third Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC '99). [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:320- [Conf]
  40. Jacques Chassin de Kergommeaux, Yves Denneulin, Thierry Gautier
    Parallel Computing for Irregular Applications. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:321- [Conf]
  41. Dean M. Tullsen, Guang R. Gao
    Multithreaded Execution Architecture and Compilation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:321- [Conf]
  42. Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
    Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:322- [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002