Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
2002 (conf/hpca/2002)

1. Timothy Chou
   The Software Industry: Ten Lessons for Long Life. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:3- [Conf]
   
2. Ed Grochowski, David Ayers, Vivek Tiwari
   Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:7-16 [Conf]
   
3. Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan
   Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:17-28 [Conf]
   
4. Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
   Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:29-42 [Conf]
   
5. Marcelo H. Cintra, Josep Torrellas
   Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:43-54 [Conf]
   
6. Pedro Marcuello, Antonio González
   Thread-Spawning Schemes for Speculative Multithreading. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:55-64 [Conf]
   
7. J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry
   Improving Value Communication for Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:65-0 [Conf]
   
8. Mariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, Yasunori Kimura
   Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:81-91 [Conf]
   
9. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
   Tuning Garbage Collection in an Embedded Java Environment. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:92-0 [Conf]
   
10. Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
    Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:107-116 [Conf]
    
11. G. Edward Suh, Srinivas Devadas, Larry Rudolph
    A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:117-0 [Conf]
    
12. Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
    The Minimax Cache: An Energy-Efficient Framework for Media Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:131-140 [Conf]
    
13. Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John
    Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:141-150 [Conf]
    
14. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar
    Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:151-0 [Conf]
    
15. Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul Shen
    Non-Vital Loads. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:165-0 [Conf]
    
16. Xavier Vera, Jingling Xue
    Let's Study Whole-Program Cache Behaviour Analytically. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:175-186 [Conf]
    
17. Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
    Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:187-196 [Conf]
    
18. Suleyman Sair, Timothy Sherwood, Brad Calder
    Quantifying Load Stream Behavior. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:197-0 [Conf]
    
19. Yiannakis Sazeides
    Modeling Value Speculation. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:211-222 [Conf]
    
20. Martin Kämpe, Per Stenström, Michel Dubois
    The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:223-232 [Conf]
    
21. Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, Mircea R. Stan
    Power Issues Related to Branch Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:233-0 [Conf]
    
22. David A. Patterson
    Recovery Oriented Computing: A New Research Agenda for a New Century. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:247- [Conf]
    
23. Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Bandwidth Adaptive Snooping. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:251-262 [Conf]
    
24. Peter Jamieson, Angelos Bilas
    CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:263-274 [Conf]
    
25. Enrique V. Carrera, Srinath Rao, Liviu Iftode, Ricardo Bianchini
    User-Level Communication in Cluster-Based Servers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:275-0 [Conf]
    
26. Mary D. Brown, Yale N. Patt
    Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:289-298 [Conf]
    
27. Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer
    Loose Loops Sink Chips. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:299-310 [Conf]
    
28. Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.
    Evaluation of a Multithreaded Architecture for Cellular Computing. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:311-322 [Conf]