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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
1995 (conf/hpca/1995)

  1. Peter R. Nuth, William J. Dally
    The Named-State Register File: Implementation and Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:4-13 [Conf]
  2. Shlomo Weiss
    Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:14-21 [Conf]
  3. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Non-Consistent Dual Register Files to Reduce Register Pressure. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:22-31 [Conf]
  4. Chunming Qiao, Rami G. Melhem
    Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:34-43 [Conf]
  5. Franck Cappello, Cécile Germain
    Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:44-53 [Conf]
  6. Anand Sivasubramaniam, Aman Singla, Umakishore Ramachandran, H. Venkateswaran
    Abstracting Network Characteristics and Locality Properties of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:54-63 [Conf]
  7. Fredrik Dahlgren, Per Stenström
    Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:68-77 [Conf]
  8. Keith I. Farkas, Norman P. Jouppi, Paul Chow
    How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:78-89 [Conf]
  9. Daniel Citron, Larry Rudolph
    Creating a Wider Bus Using Caching Techniques. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:90-99 [Conf]
  10. Ran Libeskind-Hadas, Eli Brandt
    Origin-Based Fault-Tolerant routing in the Mesh. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:102-111 [Conf]
  11. Jatin Upadhyay, Vara Varavithya, Prasant Mohapatra
    Efficient and Balanced Adaptive Routing in Two-Dimensional Meshes. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:112-121 [Conf]
  12. Chris M. Cunningham, Dimiter R. Avresky
    Fault-Tolerant Adaptive Routing for Two-Dimensional Meshes. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:122-131 [Conf]
  13. André Seznec
    DASC Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:134-143 [Conf]
  14. Kevin B. Theobald, Herbert H. J. Hum, Guang R. Gao
    A Design Frame for Hybrid Access Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:144-153 [Conf]
  15. Olivier Temam, Nathalie Drach
    Software Assistance for Data Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:154-163 [Conf]
  16. Younes M. Boura, Chita R. Das
    Modeling Virtual Channel Flow Control in Hypercubes. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:166-175 [Conf]
  17. Thomas L. Sterling, Daniel Savarese, Phillip Merkey, Jeffrey P. Gardner
    An Initial Evaluation of the Convex SPP-1000 for Earth and Space Science Application. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:176-185 [Conf]
  18. Kent Treiber, Jai Menon
    Simulation Study of Cached RAID5 Designs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:186-197 [Conf]
  19. Dhabaleswar K. Panda
    Fast Barrier Synchronization in Wormhole k-ary n-cube Networks with Multidestination Worms. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:200-209 [Conf]
  20. Stuart Fiske, William J. Dally
    Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:210-221 [Conf]
  21. Maged M. Michael, Michael L. Scott
    Implementation of Atomic Primitives on Distributed Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:222-231 [Conf]
  22. Karl Westerholz, Stephen Honal, Josef Planl, Christian Hafer
    Improving Performance by Cache Driven Memory Management. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:234-242 [Conf]
  23. Jesung Kim, Sang Lyul Min, Sanghoon Jeon, Byoungchul Ahn, Deog-Kyoon Jeong, Chong-Sang Kim
    U-Cache: A Cost-Effective Solution to the Synonym Problem. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:243-252 [Conf]
  24. Sally A. McKee, William A. Wulf
    Access Ordering and Memory-Conscious Cache Utilization. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:253-262 [Conf]
  25. Craig Anderson, Jean-Loup Baer
    Two Techniques for Improving Performance on Bus-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:264-275 [Conf]
  26. Ashley Saulsbury, Tim Wilkinson, John B. Carter, Anders Landin
    An Argument for Simple COMA. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:276-285 [Conf]
  27. Leonidas I. Kontothanassis, Michael L. Scott
    Software Cache Coherence for Large Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:286-295 [Conf]
  28. Ramaswamy Govindarajan, Shashank S. Nemawarkar, Phillip LeNir
    Design and Performance Evaluation of a Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:298-307 [Conf]
  29. Tetsuo Kawano, Shigeru Kusakabe, Rin-ichiro Taniguchi, Makoto Amamiya
    Fine-Grain Multi-Thread Processor Architecture for Massively Parallel Processing. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:308-317 [Conf]
  30. Yamin Li, Wanming Chu
    The Effects of STEF in Finely Parallel Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:318-325 [Conf]
  31. Raghu Sastry, N. Ranganathan
    A VLSI Architecture for Computer the Tree-to-Tree Distance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:330-339 [Conf]
  32. Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang
    Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:340-347 [Conf]
  33. Vivek Garg, David E. Schimmel
    Architectural Support for Inter-Stream Communication in a MSIMD System. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:348-357 [Conf]
  34. Josep Torrellas, Chun Xia, Russell L. Daigle
    Optimizing Instruction Cache Performance for Operating System Intensive Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:360-369 [Conf]
  35. Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
    Program Balance and Its Impact on High Performance RISC Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:370-379 [Conf]
  36. De-Lei Lee
    Memory Access Reordering in Vector Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:380-389 [Conf]
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