Conferences in DBLP
Peter R. Nuth , William J. Dally The Named-State Register File: Implementation and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Llosa , Mateo Valero , Eduard Ayguadé Non-Consistent Dual Register Files to Reduce Register Pressure. [Citation Graph (0, 0)][DBLP ] Conf ] Chunming Qiao , Rami G. Melhem Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Franck Cappello , Cécile Germain Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Sivasubramaniam , Aman Singla , Umakishore Ramachandran , H. Venkateswaran Abstracting Network Characteristics and Locality Properties of Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Fredrik Dahlgren , Per Stenström Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Keith I. Farkas , Norman P. Jouppi , Paul Chow How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Citron , Larry Rudolph Creating a Wider Bus Using Caching Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Ran Libeskind-Hadas , Eli Brandt Origin-Based Fault-Tolerant routing in the Mesh. [Citation Graph (0, 0)][DBLP ] Conf ] Jatin Upadhyay , Vara Varavithya , Prasant Mohapatra Efficient and Balanced Adaptive Routing in Two-Dimensional Meshes. [Citation Graph (0, 0)][DBLP ] Conf ] Chris M. Cunningham , Dimiter R. Avresky Fault-Tolerant Adaptive Routing for Two-Dimensional Meshes. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec DASC Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin B. Theobald , Herbert H. J. Hum , Guang R. Gao A Design Frame for Hybrid Access Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Temam , Nathalie Drach Software Assistance for Data Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Younes M. Boura , Chita R. Das Modeling Virtual Channel Flow Control in Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas L. Sterling , Daniel Savarese , Phillip Merkey , Jeffrey P. Gardner An Initial Evaluation of the Convex SPP-1000 for Earth and Space Science Application. [Citation Graph (0, 0)][DBLP ] Conf ] Kent Treiber , Jai Menon Simulation Study of Cached RAID5 Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Dhabaleswar K. Panda Fast Barrier Synchronization in Wormhole k-ary n-cube Networks with Multidestination Worms. [Citation Graph (0, 0)][DBLP ] Conf ] Stuart Fiske , William J. Dally Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Maged M. Michael , Michael L. Scott Implementation of Atomic Primitives on Distributed Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Karl Westerholz , Stephen Honal , Josef Planl , Christian Hafer Improving Performance by Cache Driven Memory Management. [Citation Graph (0, 0)][DBLP ] Conf ] Jesung Kim , Sang Lyul Min , Sanghoon Jeon , Byoungchul Ahn , Deog-Kyoon Jeong , Chong-Sang Kim U-Cache: A Cost-Effective Solution to the Synonym Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Sally A. McKee , William A. Wulf Access Ordering and Memory-Conscious Cache Utilization. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Anderson , Jean-Loup Baer Two Techniques for Improving Performance on Bus-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ashley Saulsbury , Tim Wilkinson , John B. Carter , Anders Landin An Argument for Simple COMA. [Citation Graph (0, 0)][DBLP ] Conf ] Leonidas I. Kontothanassis , Michael L. Scott Software Cache Coherence for Large Scale Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswamy Govindarajan , Shashank S. Nemawarkar , Phillip LeNir Design and Performance Evaluation of a Multithreaded Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuo Kawano , Shigeru Kusakabe , Rin-ichiro Taniguchi , Makoto Amamiya Fine-Grain Multi-Thread Processor Architecture for Massively Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Yamin Li , Wanming Chu The Effects of STEF in Finely Parallel Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Raghu Sastry , N. Ranganathan A VLSI Architecture for Computer the Tree-to-Tree Distance. [Citation Graph (0, 0)][DBLP ] Conf ] Youngmin Hur , Stephen A. Szygenda , E. Scott Fehr , Granville E. Ott , Sungho Kang Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Garg , David E. Schimmel Architectural Support for Inter-Stream Communication in a MSIMD System. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Torrellas , Chun Xia , Russell L. Daigle Optimizing Instruction Cache Performance for Operating System Intensive Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John , Vinod Reddy , Paul T. Hulina , Lee D. Coraor Program Balance and Its Impact on High Performance RISC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] De-Lei Lee Memory Access Reordering in Vector Processors. [Citation Graph (0, 0)][DBLP ] Conf ] 