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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
1998 (conf/hpca/1998)

  1. J. Gregory Steffan, Todd C. Mowry
    The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:2-13 [Conf]
  2. Jordi Tubella, Antonio González
    Control Speculation in Multithreaded Processors through Dynamic Loop Detection. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:14-23 [Conf]
  3. Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chung Yew
    Performance Study of a Concurrent Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:24-35 [Conf]
  4. Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal
    The Sensitivity of Communication Mechanisms to Bandwidth and Latency. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:37-46 [Conf]
  5. Manolis Katevenis, Dimitrios N. Serpanos, Emmanuel Spyridakis
    Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:47-56 [Conf]
  6. Pedro López, Juan Miguel Martínez, José Duato
    A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:57-0 [Conf]
  7. Koen Langendoen, Rutger F. H. Hofman, Henri E. Bal
    Challenging Applications on Fast Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:68-79 [Conf]
  8. David R. O'Hallaron, Jonathan Richard Shewchuk, Thomas R. Gross
    Architectural Implications of a Family of Irregular Applications. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:80-89 [Conf]
  9. Remzi H. Arpaci-Dusseau, Andrea C. Arpaci-Dusseau, David E. Culler, Joseph M. Hellerstein, David A. Patterson
    The Architectural Costs of Streaming I/O: A Comparison of Workstations, Clusters, and SMPs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:90-101 [Conf]
  10. Adrian Moga, Michel Dubois
    The Effectiveness of SRAM Network Caches in Clustered DSMs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:103-112 [Conf]
  11. Rudrajit Samanta, Angelos Bilas, Liviu Iftode, Jaswinder Pal Singh
    Home-Based SVM Protocols for SMP Clusters: Design and Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:113-124 [Conf]
  12. Daniel J. Scales, Kourosh Gharachorloo, Anshu Aggarwal
    Fine-Grain Software Distributed Shared Memory on SMP Clusters. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:125-136 [Conf]
  13. Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnaik, Marc Snir
    PRISM: An Integrated Architecture for Scalable Shared Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:140-151 [Conf]
  14. Sujoy Basu, Josep Torrellas
    Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:152-161 [Conf]
  15. Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
    Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:162-173 [Conf]
  16. Antonio González, José González, Mateo Valero
    Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:175-184 [Conf]
  17. Tien-Fu Chen
    Supporting Highly-Speculative Execution via Adaptive Branch Trees. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:185-194 [Conf]
  18. Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:195-205 [Conf]
  19. Shubhendu S. Mukherjee, Mark D. Hill
    The Impact of Data Transfer and Buffering Alternatives on Network Interface Design. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:207-218 [Conf]
  20. Ioannis Schoinas, Mark D. Hill
    Address Translation Mechanisms In Network Interfaces. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:219-230 [Conf]
  21. Kenneth Mackenzie, John Kubiatowicz, Matthew Frank, Walter Lee, Victor Lee, Anant Agarwal, M. Frans Kaashoek
    Exploiting Two-Case Delivery for Fast Protected Messaging. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:231-242 [Conf]
  22. John Kalamatianos, David R. Kaeli
    Temporal-Based Procedure Reordering for Improved Instruction Cache Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:244-253 [Conf]
  23. Marta Jiménez, José M. Llabería, Agustin Fernández
    Performance Evaluation of Tiling for the Register Level. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:254-265 [Conf]
  24. William A. Havanki, Sanjeev Banerjia, Thomas M. Conte
    Treegion Scheduling for Wide Issue Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:266-276 [Conf]
  25. Kaushik Ghosh, Allan J. Christie
    Communication Across Fault-Containment Firewalls on the SGI Origin. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:277-287 [Conf]
  26. Luiz Rodolpho Monnerat, Ricardo Bianchini
    Efficiently Adapting to Sharing Patterns in Software DSMs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:289-299 [Conf]
  27. Todd C. Mowy, Charles Q. C. Chan, Adley K. W. Lo
    Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:300-311 [Conf]
  28. Evan Speight, John K. Bennett
    Using Multicast and Multithreading to Reduce Communication in Software DSM Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:312-0 [Conf]
  29. David Abramson, Paul Logothetis, Adam Postula, Marcus Randall
    FPGA Based Custom Computing Machines for Irregular Problems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:324-333 [Conf]
  30. Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu
    Non-Stalling CounterFlow Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:334-341 [Conf]
  31. Darren Erik Vengroff, Guang R. Gao
    Partial Sampling with Reverse State Reconstruction: A New Technique for Branch Predictor Performance Estimation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:342-351 [Conf]
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