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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
1996 (conf/hpca/1996)

  1. Magnus Karlsson, Per Stenström
    Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:4-13 [Conf]
  2. Liviu Iftode, Cezary Dubnicki, Edward W. Felten, Kai Li
    Improving Release-Consistent Shared Virtual Memory Using Automatic Update. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:14-25 [Conf]
  3. Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ramakrishnan Rajamony, Willy Zwaenepoel
    A Comparison of Entry Consistency and Lazy Release Consistency Implementations. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:26-37 [Conf]
  4. Keith I. Farkas, Norman P. Jouppi, Paul Chow
    Register File Design Considerations in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:40-51 [Conf]
  5. Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
    Co-Scheduling Hardware and Software Pipelines. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:52-61 [Conf]
  6. Vijay S. Iyengar, Louise Trevillyan, Pradip Bose
    Representative Traces for Processor Models with Infinite Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:62-72 [Conf]
  7. Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh
    The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:74-84 [Conf]
  8. Chun Xia, Josep Torrellas
    Improving the Data Cache Performance of Multiprocessor Operating Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:85-94 [Conf]
  9. Anders Landin, Fredrik Dahlgren
    Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:95-105 [Conf]
  10. Hossam A. ElGindy, Arun K. Somani, Heiko Schröder, Hartmut Schmeck, Andrew Spray
    RMB - A Reconfigurable Multiple Bus Network. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:108-117 [Conf]
  11. Chunming Qiao, Yousong Mei
    On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:118-129 [Conf]
  12. Guihai Chen, Francis C. M. Lau
    Shuffle-Ring: Overcoming the Increasing Degree of Hypercube. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:130-138 [Conf]
  13. Evangelos P. Markatos, Manolis Katevenis
    Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:144-153 [Conf]
  14. Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li
    Protected, User-Level DMA for the SHRIMP Network Interface. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:154-165 [Conf]
  15. Leonidas I. Kontothanassis, Michael L. Scott
    Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:166-177 [Conf]
  16. Ran Libeskind-Hadas, Kevin Watkins, Thomas Hehre
    Fault-Tolerant Multicast Routing in the Mesh with No Virtual Channels. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:180-190 [Conf]
  17. Hyunmin Park, Dharma P. Agrawal
    A Topology-Independent Generic Methodology for Deadlock-Free Wormhole Routing. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:191-200 [Conf]
  18. Suresh Chalasani, Rajendra V. Boppana
    Fault-Tolerance with Multimodule Routers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:201-210 [Conf]
  19. Henk L. Muller, Paul W. A. Stallard, David H. D. Warren
    Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:212-221 [Conf]
  20. John A. Reisner, Tom S. Wailes
    A Cache Coherency Protocol for Optically Connected Parallel Computer Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:222-231 [Conf]
  21. Wen-jann Yang, Ramalingam Sridhar, Victor Demjanenko
    Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:232-241 [Conf]
  22. Brad Calder, Dirk Grunwald, Joel S. Emer
    Predictive Sequential Associative Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:244-253 [Conf]
  23. Thomas Alexander, Gershon Kedem
    Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:254-263 [Conf]
  24. Zarka Cvetanovic, Dileep Bhandarkar
    Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:270-280 [Conf]
  25. Roger Espasa, Mateo Valero
    Decoupled Vector Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:281-290 [Conf]
  26. Manu Gulati, Nader Bagherzadeh
    Performance Study of a Multithreaded Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:291-301 [Conf]
  27. Craig Anderson, Anna R. Karlin
    Two Adaptive Hybrid Cache Coherency Protocols. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:303-313 [Conf]
  28. Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki
    A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:314-322 [Conf]
  29. Alain Raynaud, Zheng Zhang, Josep Torrellas
    Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:323-334 [Conf]
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