Conferences in DBLP
Magnus Karlsson , Per Stenström Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. [Citation Graph (0, 0)][DBLP ] Conf ] Liviu Iftode , Cezary Dubnicki , Edward W. Felten , Kai Li Improving Release-Consistent Shared Virtual Memory Using Automatic Update. [Citation Graph (0, 0)][DBLP ] Conf ] Sarita V. Adve , Alan L. Cox , Sandhya Dwarkadas , Ramakrishnan Rajamony , Willy Zwaenepoel A Comparison of Entry Consistency and Lazy Release Consistency Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Keith I. Farkas , Norman P. Jouppi , Paul Chow Register File Design Considerations in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswamy Govindarajan , Erik R. Altman , Guang R. Gao Co-Scheduling Hardware and Software Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay S. Iyengar , Louise Trevillyan , Pradip Bose Representative Traces for Processor Models with Infinite Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Basem A. Nayfeh , Kunle Olukotun , Jaswinder Pal Singh The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Xia , Josep Torrellas Improving the Data Cache Performance of Multiprocessor Operating Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Landin , Fredrik Dahlgren Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Hossam A. ElGindy , Arun K. Somani , Heiko Schröder , Hartmut Schmeck , Andrew Spray RMB - A Reconfigurable Multiple Bus Network. [Citation Graph (0, 0)][DBLP ] Conf ] Chunming Qiao , Yousong Mei On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Guihai Chen , Francis C. M. Lau Shuffle-Ring: Overcoming the Increasing Degree of Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Evangelos P. Markatos , Manolis Katevenis Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias A. Blumrich , Cezary Dubnicki , Edward W. Felten , Kai Li Protected, User-Level DMA for the SHRIMP Network Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Leonidas I. Kontothanassis , Michael L. Scott Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Ran Libeskind-Hadas , Kevin Watkins , Thomas Hehre Fault-Tolerant Multicast Routing in the Mesh with No Virtual Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunmin Park , Dharma P. Agrawal A Topology-Independent Generic Methodology for Deadlock-Free Wormhole Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Chalasani , Rajendra V. Boppana Fault-Tolerance with Multimodule Routers. [Citation Graph (0, 0)][DBLP ] Conf ] Henk L. Muller , Paul W. A. Stallard , David H. D. Warren Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Reisner , Tom S. Wailes A Cache Coherency Protocol for Optically Connected Parallel Computer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-jann Yang , Ramalingam Sridhar , Victor Demjanenko Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses. [Citation Graph (0, 0)][DBLP ] Conf ] Brad Calder , Dirk Grunwald , Joel S. Emer Predictive Sequential Associative Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Alexander , Gershon Kedem Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zarka Cvetanovic , Dileep Bhandarkar Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Roger Espasa , Mateo Valero Decoupled Vector Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Manu Gulati , Nader Bagherzadeh Performance Study of a Multithreaded Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Anderson , Anna R. Karlin Two Adaptive Hybrid Cache Coherency Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Masafumi Takahashi , Hiroyuki Takano , Emi Kaneko , Seigo Suzuki A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Raynaud , Zheng Zhang , Josep Torrellas Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] 