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Conferences in DBLP
- Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese
Impact of Chip-Level Integration on Performance of OLTP Workloads. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:3-14 [Conf]
- Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:15-25 [Conf]
- Renato J. O. Figueiredo, José A. B. Fortes
Impact of Heterogeneity on DSM Performance. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:26-0 [Conf]
- Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis
Design of a Parallel Vector Access Unit for SDRAM Memory Systems. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:39-48 [Conf]
- Wayne A. Wong, Jean-Loup Baer
Modified LRU Policies for Improving Second-Level Cache Behavior. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:49-60 [Conf]
- Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
eXtended Block Cache. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:61-0 [Conf]
- Li-Shiuan Peh, William J. Dally
Flit-Reservation Flow Control. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:73-84 [Conf]
- Rafael Casado, Aurelio Bermúdez, Francisco J. Quiles, José L. Sánchez, José Duato
Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:85-96 [Conf]
- Ki Hwan Yum, Aniruddha S. Vaidya, Chita R. Das, Anand Sivasubramaniam
Investigating QoS Support for Traffic Mixes with the MediaWorm Router. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:97-0 [Conf]
- James Burns, Jean-Luc Gaudiot
Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight? [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:109-120 [Conf]
- Todd C. Mowry, Sherwyn R. Ramkissoon
Software-Controlled Multithreading Using Informing Memory Operations. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:121-132 [Conf]
- Ramon Canal, Joan-Manuel Parcerisa, Antonio González
Dynamic Cluster Assignment Mechanisms. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:133-0 [Conf]
- Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
High-Throughput Coherence Controllers. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:145-155 [Conf]
- Stefanos Kaxiras, Cliff Young
Coherence Communication Prediction in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:156-167 [Conf]
- Ravi Rajwar, Alain Kägi, James R. Goodman
Improving the Throughput of Synchronization by Insertion of Delays. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:168-0 [Conf]
- Marta Jiménez, José M. Llabería, Agustin Fernández
On the Performance of Hand vs. Automatically Optimized Numerical Codes. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:183-194 [Conf]
- Siddhartha Chatterjee, Sandeep Sen
Cache-Efficient Matrix Transposition. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:195-205 [Conf]
- Magnus Karlsson, Fredrik Dahlgren, Per Stenström
A Prefetching Technique for Irregular Accesses to Linked Data Structures. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:206-217 [Conf]
- Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
Reducing Code Size with Run-Time Decompression. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:218-0 [Conf]
- Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
Decoupled Value Prediction on Trace Processors. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:231-240 [Conf]
- Michael Haungs, Phil Sallee, Matthew K. Farrens
Branch Transition Rate: A New Metric for Improved Branch Classification Analysis. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:241-250 [Conf]
- Harish Patil, Joel S. Emer
Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:251-0 [Conf]
- Robert Stets, Sandhya Dwarkadas, Leonidas I. Kontothanassis, Umit Rencuzogullari, Michael L. Scott
The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:265-276 [Conf]
- Peter M. Behr, S. Pletner, Angela C. Sodan
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:277-286 [Conf]
- Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose
A DSM Architecture for a Parallel Computer Cenju-4. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:287-0 [Conf]
- Andreas Moshovos, Gurindar S. Sohi
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:301-312 [Conf]
- Henk Neefs, Hans Vandierendonck, Koenraad De Bosschere
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:313-324 [Conf]
- Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
Trace Cache Redundancy: Red & Blue Traces. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:325-0 [Conf]
- Mustafa Uysal, Anurag Acharya, Joel H. Saltz
Evaluation of Active Disks for Decision Support Databases. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:337-348 [Conf]
- Franck Cappello, Olivier Richard, Daniel Etiemble
Investigating the Performance of Two Programming Models for Clusters of SMP PCs. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:349-359 [Conf]
- Robert Bosch, Chris Stolte, Gordon Stoll, Mendel Rosenblum, Pat Hanrahan
Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:360-0 [Conf]
- Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens
Register Organization for Media Processing. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:375-386 [Conf]
- Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam
Architectural Issues in Java Runtime Systems. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:387-398 [Conf]
- Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:399-408 [Conf]
- Tzi-cker Chiueh, Prashant Pradhan
Cache Memory Design for Network Processors. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:409-0 [Conf]
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