Conferences in DBLP
Hongmei Li , Jorge Carballido , Harry H. Yu , Vladimir I. Okhmatovski , Elyse Rosenbaum , Andreas C. Cangellaris Comprehensive frequency-dependent substrate noise analysis using boundary element methods. [Citation Graph (0, 0)][DBLP ] Conf ] Eelco Schrik , Patrick Dewilde , N. P. van der Meijs Theoretical and practical validation of combined BEM/FEM substrate resistance modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Dipak Sitaram , Yu Zheng , Kenneth L. Shepard Implicit treatment of substrate and power-ground losses in return-limited inductance extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Takayasu Sakurai Minimizing power across multiple technology and design levels. [Citation Graph (0, 0)][DBLP ] Conf ] Tadahiro Kuroda Optimization and control of V DD and V TH for low-power, high-speed CMOS design. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Brodersen , Mark Horowitz , Dejan Markovic , Borivoje Nikolic , Vladimir Stojanovic Methods for true power minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Ping Lin , Yao-Wen Chang A novel framework for multilevel routing considering routability and performance. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Min Xie , Yan Zhang An enhanced multilevel routing system. [Citation Graph (0, 0)][DBLP ] Conf ] Shabbir H. Batterywala , Narendra V. Shenoy , William Nicholls , Hai Zhou Track assignment: a desirable intermediate step between global routing and detailed routing. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , Kai-Yuan Chao , D. F. Wong ECO algorithms for removing overlaps between power rails and signal wires. [Citation Graph (0, 0)][DBLP ] Conf ] Nahmsuk Oh , Rohit Kapur , Thomas W. Williams Fast seed computation for reseeding shift register in test pattern compression. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On undetectable faults in partial scan circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chen Wang , Sudhakar M. Reddy , Irith Pomeranz , Xijiang Lin , Janusz Rajski Conflict driven techniques for improving deterministic test pattern generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jia Liou , Li-C. Wang , Kwang-Ting Cheng On theoretical and practical considerations of path selection for delay fault testing. [Citation Graph (0, 0)][DBLP ] Conf ] Satnam Singh Interface specification for reconfigurable components. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Zhong , Niraj K. Jha Interconnect-aware high-level synthesis for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Srivastava , Majid Sarrafzadeh Predictability: definition, ananlysis and optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yuan , Ken Albin , Adnan Aziz , Carl Pixley Simplifying Boolean constraint solving for random simulation-vector generation. [Citation Graph (0, 0)][DBLP ] Conf ] Katarzyna Radecka , Zeljko Zilic Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Passerone , Luca de Alfaro , Thomas A. Henzinger , Alberto L. Sangiovanni-Vincentelli Convertibility verification and converter synthesis: two faces of the same coin. [Citation Graph (0, 0)][DBLP ] Conf ] James Kao , Siva Narendra , Anantha Chandrakasan Subthreshold leakage modeling and reduction techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Jianwen Zhu Symbolic pointer analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Priya Unnikrishnan , Guangyu Chen , Mahmut T. Kandemir , D. R. Mudgett Dynamic compilation for energy adaptation. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Frank Vahid Hardware/software partitioning of software binaries. [Citation Graph (0, 0)][DBLP ] Conf ] Tim (Tianming) Kong A novel net weighting algorithm for timing-driven placement. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojian Yang , Bo-Kyung Choi , Majid Sarrafzadeh Timing-driven placement using design hierarchy guided constraint generation. [Citation Graph (0, 0)][DBLP ] Conf ] Cristinel Ababei , Navaratnasothie Selvakkumaran , Kia Bazargan , George Karypis Multi-objective circuit partitioning for cutsize and path-based delay minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Paul S. Zuchowski , Christopher B. Reynolds , Richard J. Grupp , Shelly G. Davis , Brendan Cremen , Bill Troxel A hybrid ASIC and FPGA architecture. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Lackey , Paul S. Zuchowski , Thomas R. Bednar , Douglas W. Stout , Scott W. Gould , John M. Cohn Managing power and performance for System-on-Chip designs using Voltage Islands. [Citation Graph (0, 0)][DBLP ] Conf ] Tanay Karnik , Shekhar Borkar , Vivek De Sub-90nm technologies: challenges and opportunities for CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Pacelli A local circuit topology for inductive parasitics. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Hao Chen , Clement Luk , Hyungsuk Kim , Charlie Chung-Ping Chen INDUCTWISE: inductance-wise interconnect simulator and extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Haitian Hu , David Blaauw , Vladimir Zolotov , Kaushik Gala , Min Zhao , Rajendran Panda , Sachin S. Sapatnekar A precorrected-FFT method for simulating on-chip inductance. [Citation Graph (0, 0)][DBLP ] Conf ] Piet Vanassche , Georges G. E. Gielen , Willy M. C. Sansen On the difference between two widely publicized methods for analyzing oscillator phase behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Francken , Martin Vogels , Ewout Martens , Georges G. E. Gielen A behavioral simulation tool for continuous-time delta sigma modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury Making Fourier-envelope simulation robust. [Citation Graph (0, 0)][DBLP ] Conf ] Soha Hassoun , Charles J. Alpert , Meera Thiagarajan Optimal buffered routing path constructions for single and multiple clock domain systems. [Citation Graph (0, 0)][DBLP ] Conf ] Muzhou Shao , D. F. Wong , Youxin Gao , Li-Pen Yuan , Huijing Cao Shaping interconnect for uniform current density. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Bao Liu , Ion I. Mandoiu Non-tree routing for reliability and yield improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Pasquale Cocchini Concurrent flip-flop and repeater insertion for high performance integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Lin , Lawrence T. Pileggi Throughput-driven IC communication fabric synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Harshit K. Shah , Pun Shiu , Brian Bell , Mamie Aldredge , Namarata Sopory , Jeff Davis Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Ramnath , Frederic Neuveux , Mokhtar Hirech , Felix Ng Test-model based hierarchical DFT synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoding Chen , Michael S. Hsiao Characteristic faults and spectral information for logic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu A novel scan architecture for power-efficient, rapid test. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Vancorenland , Philippe Coppejans , Wouter De Cock , Paul Leroux , Michiel Steyaert Optimization of a fully integrated low power CMOS GPS receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Adil Koukab , Kaustav Banerjee , Michel J. Declercq Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. [Citation Graph (0, 0)][DBLP ] Conf ] Maria del Mar Hershenson Design of pipeline analog-to-digital converters via geometric programming. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Daniel , Alberto L. Sangiovanni-Vincentelli , Jacob White Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Escovar , Roberto Suaya Transmission line design of clock trees. [Citation Graph (0, 0)][DBLP ] Conf ] Guoan Zhong , Cheng-Kok Koh , Kaushik Roy On-chip interconnect modeling by wire duplication. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew M. Ziegler , Mircea R. Stan A Case for CMOS/nano co-design. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek V. Shende , Aditya K. Prasad , Igor L. Markov , John P. Hayes Reversible logic circuit synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Bikram Baidya , Tamal Mukherjee Extraction and LVS for mixed-domain integrated MEMS layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Jing , Tamal Mukherjee , Gary K. Fedder Schematic-based lumped parameterized behavioral modeling for suspended MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Ketkar , Sachin S. Sapatnekar Standby power optimization via transistor sizing and dual threshold voltage assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Anoop Iyer , Diana Marculescu Power efficiency of voltage scaling in multiple clock, multiple voltage cores. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Vujkovic , Carl Sechen Optimized power-delay curve generation for standard cell ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiran Tennakoon , Carl Sechen Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. [Citation Graph (0, 0)][DBLP ] Conf ] Xun Liu , Marios C. Papaefthymiou A Markov chain sequence generator for power macromodeling. [Citation Graph (0, 0)][DBLP ] Conf ] Lipeng Cao Circuit power estimation using pattern recognition techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw Estimation of signal arrival times in the presence of delay noise. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Lavin , Lars Liebmann CAD computation for manufacturability: can we save VLSI technology from itself? [Citation Graph (0, 0)][DBLP ] Conf ] Michael Butts , André DeHon , Seth Copen Goldstein Molecular electronics: devices, systems and tools for gigagate, gigabit chips. [Citation Graph (0, 0)][DBLP ] Conf ] Lintao Zhang , Sharad Malik Conflict driven learning in a quantified Boolean Satisfiability solver. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Arathi Ramani , Igor L. Markov , Karem A. Sakallah Generic ILP versus specialized 0-1 ILP: an update. [Citation Graph (0, 0)][DBLP ] Conf ] Farzan Fallah Binary time-frame expansion. [Citation Graph (0, 0)][DBLP ] Conf ] Shihhsien S. Kuo , Michael D. Altman , Jaydeep P. Bardhan , Bruce Tidor , Jacob K. White Fast methods for simulation of biomolecule electrostatics. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Li , Narayan R. Aluru Efficient mixed-domain analysis of electrostatic MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Yehia Massoud , Jacob White FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas C. Lemke , Lars Hedrich , Erich Barke Analog circuit sizing based on formal methods using affine arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgio Biagetti , Simone Orcioni , L. Signoracci , Claudio Turchetti , Paolo Crippa , Michele Alessandrini SiSMA: a statistical simulator for mismatch analysis of MOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Florin Balasa , Sarat C. Maruvada , Karthik Krishnamoorthy Efficient solution space exploration based on segment trees in analog placement with symmetry constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jinjun Xiong , Jun Chen , James Ma , Lei He Post global routing RLC crosstalk budgeting. [Citation Graph (0, 0)][DBLP ] Conf ] Rouying Zhan , Haigang Feng , Qiong Wu , Guang Chen , Xiaokang Guan , Albert Z. Wang A technology-independent CAD tool for ESD protection device extraction: ESDExtractor. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiqi Tian , Ronggang Yu , Xiaoping Tang , D. F. Wong On mask layout partitioning for electron projection lithography. [Citation Graph (0, 0)][DBLP ] Conf ] Sasha Novakovsky , Shy Shyman , Ziyad Hanna High capacity and automatic functional extraction tool for industrial VLSI circuit designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hee-Hwan Kwak , In-Ho Moon , James H. Kukula , Thomas R. Shiple Combinational equivalence checking through function transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Yang , Amit Goel GSTE through a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Robert K. Brayton Whirlpool PLAs: a regular logic structure and their synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhakar Kudva , Andrew Sullivan , William E. Dougherty Metrics for structural logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Robert K. Brayton Simplification of non-deterministic multi-valued networks. [Citation Graph (0, 0)][DBLP ] Conf ] Chao Huang , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha High-level synthesis of distributed logic-memory architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda , Lakshmikantam Chitturi An energy-conscious algorithm for memory port allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Sambuddhi Hettiaratchi , Peter Y. K. Cheung , Thomas J. W. Clarke Energy efficient address assignment through minimized memory row switching. [Citation Graph (0, 0)][DBLP ] Conf ] Pinhong Chen , Yuji Kukimoto , Kurt Keutzer Refining switching window by time slots for crosstalk noise calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Zolotov , David Blaauw , Supamas Sirichotiyakul , Murat R. Becer , Chanhee Oh , Rajendran Panda , Amir Grinshpon , Rafi Levy Noise propagation and failure criteria for VLSI designs. [Citation Graph (0, 0)][DBLP ] Conf ] Li Ding 0002 , David Blaauw , Pinaki Mazumder Efficient crosstalk noise modeling using aggressor and tree reductions. [Citation Graph (0, 0)][DBLP ] Conf ] María C. Molina , José M. Mendías , Román Hermida Bit-level scheduling of heterogeneous behavioural specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Gi Lyuh , Taewhan Kim , Ki-Wook Kim Coupling-aware high-level interconnect synthesis for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Junhyung Um , Jae-Hoon Kim , Taewhan Kim Layout-driven resource sharing in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Liu , Chandramouli V. Kashyap , Charles J. Alpert A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Larry McMurchie , Carl Sechen WTA: waveform-based timing analysis for deep submicron circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jindrich Zejda , Paul Frain General framework for removal of clock network pessimism. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Synthesis of custom processors based on extensible platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-eun Lee , Kiyoung Choi , Nikil Dutt Efficient instruction encoding for automatic instruction set design of configurable ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] Susan Cotterell , Frank Vahid Synthesis of customized loop caches for core-based embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xinping Zhu , Sharad Malik A hierarchical modeling framework for on-chip communication architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Joey Y. Lin , Wangning Long A new enhanced SPFD rewiring algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Subarnarekha Sinha , Alan Mishchenko , Robert K. Brayton Topologically constrained logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Victor N. Kravets , Karem A. Sakallah Resynthesis of multi-level circuits under tight constraints using symbolic optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Kimura , Takashi Horiyama , Masaki Nakanishi , Hirotsugu Kajihara Folding of logic functions and its application to look up table compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Sorin Manolache , Petru Eles , Zebo Peng Schedulability analysis of multiprocessor real-time applications with stochastic task execution times. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Rong , Massoud Pedram Battery-aware power management based on Markovian decision processes. [Citation Graph (0, 0)][DBLP ] Conf ] Weiping Liao , Joseph M. Basile , Lei He Leakage power modeling and reduction with data retention. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Martin , Krisztián Flautner , Trevor N. Mudge , David Blaauw Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Bren Mochocki , Xiaobo Sharon Hu , Gang Quan A realistic variable voltage scheduling model for real-time applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kihwan Choi , Karthik Dantu , Wei-Chung Cheng , Massoud Pedram Frame-based dynamic voltage and frequency scaling for a MPEG decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Malgorzata Marek-Sadowska Congestion minimization during placement without estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Gi-Joon Nam , Paul Villarrubia Free space management for cut-based placement. [Citation Graph (0, 0)][DBLP ] Conf ] Deshanand P. Singh , Stephen Dean Brown Incremental placement for layout driven optimizations on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Zheng , Lawrence T. Pileggi Robust and passive model order reduction for circuits containing susceptance elements. [Citation Graph (0, 0)][DBLP ] Conf ] Yehea I. Ismail Efficient model order reduction via multi-node moment matching. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos P. Coelho , Joel R. Phillips , Luis Miguel Silveira Optimization based passive constrained fitting. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Biere , Wolfgang Kunz SAT and ATPG: Boolean engines for formal hardware verification. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wei Jim Chang , Malgorzata Marek-Sadowska ATPG-based logic synthesis: an overview. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , John Cohn The A to Z of SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] 