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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
1993 (conf/iccad/1993)

  1. Mehrdad Mojtahedi, Walter Geisselhardt
    New methods for parallel pattern fast fault simulation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:2-5 [Conf]
  2. Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab
    Fault behavior dictionary for simulation of device-level transients. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:6-9 [Conf]
  3. Hyung Ki Lee, Dong Sam Ha
    New methods of improving parallel fault simulation in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:10-17 [Conf]
  4. Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
    Exploiting hardware sharing in high-level synthesis for partial scan optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:20-25 [Conf]
  5. Lisa Guerra, Miodrag Potkonjak, Jan M. Rabaey
    High level synthesis for reconfigurable datapath structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:26-29 [Conf]
  6. Haidar Harmanani, Christos A. Papachristou
    An improved method for RTL synthesis with testability tradeoffs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:30-35 [Conf]
  7. Hiroshige Fujii, Goichi Ootomo, Chikahiro Hori
    Interleaving based variable ordering methods for ordered binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:38-41 [Conf]
  8. Richard Rudell
    Dynamic variable ordering for ordered binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:42-47 [Conf]
  9. Hiroyuki Ochi, Koichi Yasuoka, Shuzo Yajima
    Breadth-first manipulation of very large binary-decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:48-55 [Conf]
  10. S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, T. Savarino, Dean P. Neikirk, Lawrence T. Pillage
    An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:58-65 [Conf]
  11. Eli Chiprout, Hansruedi Heeb, Michel S. Nakhla, Albert E. Ruehli
    Simulating 3-D retarded interconnect models using complex frequency hopping (CFH). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:66-72 [Conf]
  12. Jaebum Lee, Eugene Shragowitz, David Poli
    Bounds on net lengths for high-speed PCB. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:73-76 [Conf]
  13. Hua Xue, Chennian Di, Jochen A. G. Jess
    A net-oriented method for realistic fault analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:78-83 [Conf]
  14. Shambhu J. Upadhyaya, Liang-Chi Chen
    On-chip test generation for combinational circuits by LFSR modification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:84-87 [Conf]
  15. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Fault-based automatic test generator for linear analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:88-91 [Conf]
  16. Hyuk-Jae Jang, Barry M. Pangrle
    A grid-based approach for connectivity binding with geometric costs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:94-99 [Conf]
  17. Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
    Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:100-103 [Conf]
  18. Elke A. Rundensteiner
    Design tool integration using object-oriented database views. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:104-107 [Conf]
  19. Jason Cong, Yuzheng Ding
    Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:110-114 [Conf]
  20. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Cube-packing and two-level minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:115-122 [Conf]
  21. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-optimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:123-127 [Conf]
  22. Chih-Po Wen, Katherine A. Yelick
    Parallel timing simulation on a distributed memory multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:130-135 [Conf]
  23. Anirudh Devgan, Ronald A. Rohrer
    Event driven adaptively controlled explicit simulation of integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:136-140 [Conf]
  24. Richard J. Trihy, Ronald A. Rohrer
    Simulating sigma-delta modulators in AWEswit. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:141-144 [Conf]
  25. Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
    Practical applications of an efficient time separation of events algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:146-151 [Conf]
  26. Timothy M. Burks, Karem A. Sakallah
    Min-max linear programming and the timing analysis of digital circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:152-155 [Conf]
  27. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Minimum padding to satisfy short path constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:156-161 [Conf]
  28. Hyunchul Shin, Chunghee Kim, Wonjong Kim, Myoungsub Oh, Kwangjoon Rhee, Seogyun Choi, Heasoo Chung
    A combined hierarchical placement algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:164-169 [Conf]
  29. Wern-Jieh Sun, Carl Sechen
    Efficient and effective placement for very large circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:170-177 [Conf]
  30. Chih-Liang Eric Cheng, Ching-yen Ho
    SEFOP: a novel approach to data path module placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:178-181 [Conf]
  31. Thomas Tamisier
    Computing the observable equivalence relation of a finite state machine. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:184-187 [Conf]
  32. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic decision diagrams and their applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:188-191 [Conf]
  33. Aarti Gupta, Allan L. Fisher
    Representation and symbolic manipulation of linearly inductive Boolean functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:192-199 [Conf]
  34. Dinesh D. Gaitonde, Duncan M. Hank Walker
    Test quality and yield analysis using the DEFAM defect to fault mapper. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:202-205 [Conf]
  35. Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang
    Convexity-based algorithms for design centering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:206-209 [Conf]
  36. Julie Chen, Andrew T. Yang
    Style: a technology-independent approach to statistical design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:210-214 [Conf]
  37. Kerry S. Lowe, P. Glenn Gulak
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:216-219 [Conf]
  38. Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
    A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:220-223 [Conf]
  39. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Efficient estimation of dynamic power consumption under a real delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:224-228 [Conf]
  40. Massoud Pedram, Bahman S. Nobandegani, Bryan Preas
    Architecture and routability analysis for row-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:230-235 [Conf]
  41. Gabriele Saucier, Daniel R. Brasen, J. P. Hiol
    Partitioning with cone structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:236-239 [Conf]
  42. Enric Pastor, Jordi Cortadella
    Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:250-254 [Conf]
  43. Kenneth Y. Yun, David L. Dill
    Unifying synchronous/asynchronous state machine synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:255-260 [Conf]
  44. Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng
    Efficient verification of determinate speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:261-267 [Conf]
  45. Mark W. Reichelt, Andrew Lumsdaine, Jacob K. White
    Accelerated waveform methods for parallel transient simulation of semiconductor devices. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:270-274 [Conf]
  46. Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
    An accurate grid local truncation error for device simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:275-282 [Conf]
  47. X. Cai, H. Yie, P. Osterberg, J. Gilbert, Stephen D. Senturia, Jacob K. White
    A relaxation/multipole-accelerated scheme for self-consistent electromechanical analysis of complex 3-D microelectromechanical structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:283-286 [Conf]
  48. Brian Lockyear, Carl Ebeling
    The practical application of retiming to the design of high-performance systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:288-295 [Conf]
  49. Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
    Performance-driven partitioning using retiming and replication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:296-299 [Conf]
  50. Alexander T. Ishii
    Retiming gated-clocks and precharged circuit structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:300-307 [Conf]
  51. Luis Entrena, Kwang-Ting Cheng
    Sequential logic optimization by redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:310-315 [Conf]
  52. Yosinori Watanabe, Robert K. Brayton
    The maximum set of permissible behaviors for FSM networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:316-320 [Conf]
  53. Huey-Yih Wang, Robert K. Brayton
    Input don't care sequences in FSM networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:321-328 [Conf]
  54. Christopher Michael, Christopher J. Abel, C. S. Teng
    A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:330-333 [Conf]
  55. Pradip Mandal, V. Visvanathan
    Macromodeling of the A.C. characteristics of CMOS Op-amps. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:334-340 [Conf]
  56. Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli
    Nyquist data converter testing and yield analysis using behavioral simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:341-348 [Conf]
  57. Andrea Casotto
    Run-time requirement tracing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:350-355 [Conf]
  58. K. Olav ten Bosch, Pieter van der Wolf, Peter Bingley
    A flow-based user interface for efficient execution of the design cycle. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:356-363 [Conf]
  59. Eric J. Golin, Annette C. Feng, Linus Huang, Eric Hughes
    A visual design environment. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:364-367 [Conf]
  60. Shantanu Dutt
    New faster Kernighan-Lin-type graph-partitioning algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:370-377 [Conf]
  61. Mark Beardslee, Alberto L. Sangiovanni-Vincentelli
    An algorithm for improving partitions of pin-limited multi-chip systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:378-385 [Conf]
  62. Majid Sarrafzadeh
    Transforming an arbitrary floorplan into a sliceable one. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:386-389 [Conf]
  63. Wolfgang Ecker, M. Hofmeister
    State look ahead technique for cycle optimization of interacting finite state Moore machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:392-397 [Conf]
  64. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Retiming sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:398-402 [Conf]
  65. Gary D. Hachtel, Fabio Somenzi
    A symbolic algorithm for maximum flow in 0-1 networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:403-406 [Conf]
  66. Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli
    Generalized constraint generation for analog circuit design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:408-414 [Conf]
  67. Bulent Basaran, Rob A. Rutenbar, L. Richard Carley
    Latchup-aware placement and parasitic-bounded routing of custom analog cells. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:415-421 [Conf]
  68. Nishath K. Verghese, Sang-Soo Lee, David J. Allstot
    A unified approach to simulating electrical and thermal substrate coupling interactions in ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:422-426 [Conf]
  69. Irith Pomeranz, Sudhakar M. Reddy
    Test generation for path delay faults based on learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:428-435 [Conf]
  70. Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
    Test generation for multiple faults based on parallel vector pair analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:436-439 [Conf]
  71. Debashis Bhattacharya, Prathima Agrawal
    Boolean algebraic test generation using a distributed system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:440-443 [Conf]
  72. Steve C.-Y. Huang, Wayne Wolf
    Scheduling a minimum dependence in FSMs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:446-449 [Conf]
  73. Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee
    High throughput pipelined data path synthesis by conserving the regularity of nested loops. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:450-453 [Conf]
  74. Adwin H. Timmer, Jochen A. G. Jess
    Execution interval analysis under resource constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:454-459 [Conf]
  75. Alok Jain, Randal E. Bryant
    Inverter minimization in multi-level logic networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:462-465 [Conf]
  76. K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati
    A simple algorithm for fanout optimization using high-performance buffer libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:466-471 [Conf]
  77. Robert N. Mayo, Hervé J. Touati
    Boolean matching for full-custom ECL gates. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:472-477 [Conf]
  78. Kai Zhu, D. F. Wong, Yao-Wen Chang
    Switch module design with application to two-dimensional segmentation design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:480-485 [Conf]
  79. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:486-490 [Conf]
  80. William Swartz, Carl Sechen
    A new generalized row-based global router. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:491-498 [Conf]
  81. Irith Pomeranz, Sudhakar M. Reddy
    On diagnosis and correction of design errors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:500-507 [Conf]
  82. Paul G. Ryan, W. Kent Fuchs, Irith Pomeranz
    Fault dictionary compression and equivalence class computation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:508-511 [Conf]
  83. Yasushi Koseko, Takuji Ogihara, Shinichi Murai
    Tri-state bus conflict checking method for ATPG using BDD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:512-515 [Conf]
  84. Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
    Instruction set mapping for performance optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:518-521 [Conf]
  85. Werner Geurts, Francky Catthoor, Hugo De Man
    Quadratic zero-one programming based synthesis of application specific data paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:522-525 [Conf]
  86. Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi
    An ASIP instruction set optimization algorithm with functional module sharing constraint. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:526-532 [Conf]
  87. Daniel Brand
    Verification of large synthesized designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:534-537 [Conf]
  88. Wolfgang Kunz
    HANNIBAL: an efficient tool for logic verification based on recursive learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:538-543 [Conf]
  89. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
    Probabilistic construction and manipulation of free Boolean diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:544-583 [Conf]
  90. Peter Marwedel
    Tree-based mapping of algorithms to predefined structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:586-593 [Conf]
  91. Ing-Jer Huang, Alvin M. Despain
    Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:594-599 [Conf]
  92. Raj S. Mitra, Biswaroop Guha, Anupam Basu
    Rapid prototyping of microprocessor-based systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:600-603 [Conf]
  93. Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh
    Boolean factorization using multiple-valued minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:606-611 [Conf]
  94. Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
    Modeling hierarchical combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:612-617 [Conf]
  95. Sharad Malik
    Analysis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:618-625 [Conf]
  96. Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
    Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:628-633 [Conf]
  97. Jason Cong, Kwok-Shing Leung
    Optimal wiresizing under the distributed Elmore delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:634-639 [Conf]
  98. Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita
    An efficient algorithm for the net matching problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:640-644 [Conf]
  99. Chien-In Henry Chen, Joel T. Yuen
    Logic partitioning to pseudo-exhaustive test for BIST design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:646-649 [Conf]
  100. Dipanwita Roy Chowdhury, Supratik Chakraborty, B. Vamsi, B. Pal Chaudhuri
    Cellular automata based synthesis of easily and fully testable FSMs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:650-653 [Conf]
  101. Meryem Marzouki, Marcelo Lubaszewski, Mohamed Hedi Touati
    Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:654-657 [Conf]
  102. Tilman Kolks, Bill Lin, Hugo De Man
    Sizing and verification of communication buffers for communicating processes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:660-664 [Conf]
  103. Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
    Buffer assignment for data driven architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:665-668 [Conf]
  104. Florin Balasa, Francky Catthoor, Hugo De Man
    Exact evaluation of memory size for multi-dimensional signal processing systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:669-672 [Conf]
  105. Ted Stanion, Carl Sechen
    Maximum projections of don't care conditions in a Boolean network. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:674-679 [Conf]
  106. Dirk Möller, Janett Mohnke, Michael Weber
    Detection of symmetry of Boolean functions represented by ROBDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:680-684 [Conf]
  107. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
    FGILP: an integer linear program solver based on function graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:685-689 [Conf]
  108. Tong Gao, C. L. Liu
    Minimum crosstalk channel routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:692-696 [Conf]
  109. Kamal Chaudhary, Akira Onozawa, Ernest S. Kuh
    A spacing algorithm for performance enhancement and cross-talk reduction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:697-702 [Conf]
  110. Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang
    A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:703-708 [Conf]
  111. Sridhar Narayanan, Melvin A. Breuer
    Reconfigurable scan chains: a novel approach to reduce test application time. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:710-715 [Conf]
  112. Ben Mathew, Daniel G. Saab
    Augmented partial reset. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:716-719 [Conf]
  113. Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
    Merging multiple FSM controllers for DFT/BIST hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:720-725 [Conf]
  114. Paul E. R. Lippens, Jef L. van Meerbergen, Wim F. J. Verhaegh, Albert van der Werf
    Allocation of multiport memories for hierarchical data stream. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:728-735 [Conf]
  115. Kamlesh Rath, M. Esen Tuna, Steven D. Johnson
    Behavior tables: a basis for system representation and transformational system synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:736-740 [Conf]
  116. Lawrence F. Arnstein, Donald E. Thomas
    A general consistency technique for increasing the controllability of high level synthesis tools. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:741-744 [Conf]
  117. Peter Dahlgren, Peter Lidén
    Efficient modeling of switch-level networks containing undetermined logic node states. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:746-752 [Conf]
  118. Russell Kao, Mark Horowitz
    Piecewise linear models for Rsim. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:753-758 [Conf]
  119. Yun Sik Lee, Peter M. Maurer
    Parallel multi-delay simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:759-762 [Conf]
  120. A. J. van Genderen, N. P. van der Meijs
    Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:764-769 [Conf]
  121. Mario A. Lopez, Ravi Janardan, Sartaj K. Sahni
    A fast algorithm for VLSI net extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:770-774 [Conf]
  122. Takumi Okamoto, Masaki Ishikawa, Tomoyuki Fujita
    A new feed-through assignment algorithm based on a flow model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:775-778 [Conf]
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