Conferences in DBLP
Chuck Kring , A. Richard Newton A Cell-Replicating Approach to Minicut-Based Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli On Clustering for Minimum Delay/Area. [Citation Graph (0, 0)][DBLP ] Conf ] Lars W. Hagen , Andrew B. Kahng Fast Spectral Methods for Ratio Cut Partitioning and Clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Jaidip Singh , Resve A. Saleh iMACSIM: A Program for Multi-Level Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Miguel Silveira , Jacob White , Steven Leeb A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] David Bedrosian , Jiri Vlach An Accelerated Steady-State Method for Networks with Internally Controlled Switches. [Citation Graph (0, 0)][DBLP ] Conf ] James J. Kim , Fadi J. Kurdahi , Nohbyung Park Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Allen C.-H. Wu , Viraphol Chaiyakul , Daniel Gajski Layout-Area Models for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Zheng Lin , Cheng-Tsung Hwang , Yu-Chin Hsu Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Gao , Pravo M. Vaidya , C. L. Liu A New Performance Driven Placement Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Srinivasan , Kamal Chaudhary , Ernest S. Kuh RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Ting Wu , Andrew Lim , David Hung-Chang Du Wafer Packing for Full Mask Exposure Fabrication. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Gil Choi , Chong-Min Kyung A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury , A. Richard Newton , Donald O. Pederson An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dong H. Xie , Michel S. Nakhla Delay and Crosstalk Simulation of High-Speed VLSI Interconnects with Nonlinear Terminations. [Citation Graph (0, 0)][DBLP ] Conf ] Hansruedi Heeb , Albert E. Ruehli Retarded Models for PC Board Interconnects - Or How the Speed of Light Affects your SPICE Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Nanda Gopal , Dean P. Neikirk , Lawrence T. Pillage Evaluating RC-Interconnect Using Moment-Matching Approximations. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi The Effects of False Paths in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Taewhan Kim , Jane W.-S. Liu , C. L. Liu A Scheduling Algorithm for Conditional Resource Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Jan M. Rabaey Optimizing Resource Utilization Using Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Loganath Ramachandran , Daniel Gajski An Algorithm for Component Selection in Performance Optimized Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] T. W. Her , D. F. Wong Optimal Module Implementation and Its Application to Transistor Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Amnon Baron Cohen , Michael Shechory Track Assignment in the Pathway Datapath Layout Assembler. [Citation Graph (0, 0)][DBLP ] Conf ] H. M. A. M. Arts , Jos T. J. van Eijndhoven , Leon Stok Flexible Block-Multiplier Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Kartikeya Mayaram , Ping Yang , Jue-Hsien Chern Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Lumsdaine , Mark W. Reichelt , Jacob White Conjugate Direction Waveform Methods for Transient Two-Dimensional Simulation for MOS Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Jung Chen , Jyuo-Min Shyu , Wu-Shiung Feng Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yosinori Watanabe , Robert K. Brayton Heuristic Minimazation of Multiple-Valued Relations. [Citation Graph (0, 0)][DBLP ] Conf ] Arlindo L. Oliveira , Alberto L. Sangiovanni-Vincentelli LSAT-An Algorithm for the Synthesis of Two Level Threshold Gate Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram , Narasimha B. Bhat Layout Driven Logic Restructuring/Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Milo , Smadar Nehab Data Framework for VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , P. Murugavel , M. Poornima SLIM: A System for ASIC Library Management. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus D. Müller-Glaser , K. Kirsch , K. Neusinger Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management. [Citation Graph (0, 0)][DBLP ] Conf ] Mani B. Srivastava , Robert W. Brodersen Rapid-Prototyping of Hardware and Software in a Unified Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , Stephen W. Director Improved Methods for IC Yield and Quality Optimization Using Surface Integrals. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Ho Shih , Yusuf Leblebici , Sung-Mo Kang New Simulation Methods for MOS VLSI Timing and Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Antreich , Helmut E. Graeb Circuit Optimization Driven by Worst-Case Distances. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Styblinski , J. C. Zhang Circuit Performance Variability Reduction: Principles, Problems, and Practical Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer , Sharad Malik Delay Computation in Combinational Logic Circuits: Theory and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Alexander Saldanha , Paul R. Stephan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli , Sartaj Sahni Performance Enhancement through the Generalized Bypass Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Hervé J. Touati , Hamid Savoj , Robert K. Brayton Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Grüning , Udo Mahlstedt , Hartmut Koopmeiners DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Marzouki , F. L. Vargas Knowledge-Based Debugging of ASICs: Real Case Study and Performance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Hsing Chen , Chienwen Wu , Daniel G. Saab BETA: Behavioral Testability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hsi-Chuan Chen , David Hung-Chang Du Path Sensitization in Critical Path Problem. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva , Karem A. Sakallah , Luís M. Vidigal FPD - An Environment for Exact Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Shiang-Tang Huang , Tai-Ming Parng , Jyuo-Min Shyu A New Approach to Solving False Path Problem in Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] C. Duff , Gabriele Saucier State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. [Citation Graph (0, 0)][DBLP ] Conf ] Biswadip Mitra , Preeti Ranjan Panda , Parimal Pal Chaudhuri A Flexible Scheme for State Assignment Based on Characteristics of the FSM. [Citation Graph (0, 0)][DBLP ] Conf ] David Binger , David Knapp Encoding Multiple Outputs for Improved Column Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Debaditya Mukherjee , Charles Njinda , Melvin A. Breuer Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-In Henry Chen BISTSYN - A Built-In Self-Test Synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Warren H. Debany Jr. , Carlos R. P. Hartmann , Pramod K. Varshney , Kishan G. Mehrotra Comparison of Random Test Vector Generation Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Castro Alves , Michael Nicolaidis , P. Lestrat , Bernard Courtois Built-In Self-Test for Multi-Port RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Jay B. Brockman , Stephen W. Director The Hercules CAD Task Management System. [Citation Graph (0, 0)][DBLP ] Conf ] Moon-Jung Chung , Sangchul Kim The Configuration Management for Version Control in an Object-Oriented VHDL Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jukka Lahti , Matti Sipola , Jorma Kivelä SADE: A Graphical Tool for VHDL-Based System Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjiv Narayan , Frank Vahid , Daniel Gajski System Specification and Synthesis with the SpecCharts Language. [Citation Graph (0, 0)][DBLP ] Conf ] J. Vanhoof , Ivo Bolsens , Hugo De Man Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Imtiaz Ahmad , C. Y. Roger Chen Post-Processor for Data Path Synthesis Using Multiport Memories. [Citation Graph (0, 0)][DBLP ] Conf ] F. Depuydt , Gert Goossens , Hugo De Man Clustering Techniques for Register Optimization During Scheduling Preprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] Gerben Essink , Emile H. L. Aarts , R. van Dongen , P. van Gerwen , Jan H. M. Korst , Kees A. Vissers Scheduling in Programmable Video Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Georg Pelz , Uli Roettcher Circuit Comparison by Hierarchical Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Keh-Jeng Chang , Soo-Young Oh , Ken Lee HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Yoshitome Hierarchical Analyzer for VLSI Power Supply Networks Based on a New Reduction Method. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Grodstein , Nick Rethman , Rahul Razdan , Gabriel P. Bischoff Automatic Detection of MOS Synchronizers for Timing Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Stewart , Jacques Benkoski Static Timing Analysis Using Interval Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Ren Liu , Hsi-Chuan Chen , David Hung-Chang Du The Calculation of Signal Stable Ranges in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Nowick , David L. Dill Automatic Synthesis of Locally-Clocked Asynchronous State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Cho W. Moon , Paul R. Stephan , Robert K. Brayton Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Synthesis for Testability Techniques for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Sekiyama , Yasuyuki Fujihara , Terumine Hayashi , Mitsuho Seki , Jiro Kusuhara , Kazuhiko Iijima , Masahiro Takakura , Koji Fukatani Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Ren-Song Tsay Exact Zero Skew. [Citation Graph (0, 0)][DBLP ] Conf ] Tsukasa Yamauchi , Akio Ishizuka , Toshiyuki Nakata , Nobuyuki Nishiguchi , Nobuhiko Koike PROTON: A Parallel Detailed Router on an MIMD Parallel Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Jayaraman , Rob A. Rutenbar A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew T. Yang , Yu-Hsu Chang Bipolar Timing Modeling Including Interconnects Based on Parametric Correction. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Khordoc , Mario Dufresne , Eduard Cerny A Stimulus/Response System Based on Hierarchical Timing Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid , Daniel Gajski Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Münzner , Günter Hemme Converting Combinational Circuits into Pipelined Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng An ATPG-Based Approach to Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Pixley , Gary Beihl Calculating Resetability and Reset Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Filip Van Aelten , Jonathan Allen , Srinivas Devadas Verification of Relations Between Synchronous Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Edward W. Y. Liu , Alberto L. Sangiovanni-Vincentelli , Georges G. E. Gielen , Paul R. Gray A Behavioral Representation for Nyquist Rate A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Prabir C. Maulik , L. Richard Carley Automating Analog Circuit Design using Constrained Optimization Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Cohn , David J. Garrod , Rob A. Rutenbar , L. Richard Carley Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Janak H. Patel A Fault Oriented Partial Scan Design Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Yang Jou , Kwang-Ting Cheng Timing-Driven Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Gupta , Melvin A. Breuer Ordering Storage Elements in a Single Scan Chain. [Citation Graph (0, 0)][DBLP ] Conf ] James H. Kukula , Srinivas Devadas Finite State Machine Decomposition by Transition Pairing. [Citation Graph (0, 0)][DBLP ] Conf ] June-Kyung Rho , Gary D. Hachtel , Fabio Somenzi Don't Care Sequences and the Optimization of Interacting Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Keisuke Bekki , Tohru Nagai , Nobuhiro Hamada , Tsuguo Shimizu , Noriharu Hiratsuka , Kazumasa Shima An Automatic Finite State Machine Synthesis Using Temporal Logic Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Nancy D. Holmes , Naveed A. Sherwani , Majid Sarrafzadeh Algorithms for Three-Layer Over-The-Cell Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Terai , Kazuhiro Takahashi , Kazuo Nakajima , Koji Sato A New Model for Over-The-Cell Channel Routing with Three Layers. [Citation Graph (0, 0)][DBLP ] Conf ] Yachyang Sun , Sai-keung Dong , Shinji Sato , C. L. Liu A Channel Router for Single Layer Customization Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Cliff Yungchin Hou , C. Y. Roger Chen A Hierarchical Methodology to Improve Channel Routing by Pin Permutation. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Ho Lee , Sudhakar M. Reddy A New Test Generation Method for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy , Lakshmi N. Reddy Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Jaushin Lee , Janak H. Patel A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Seh-Woong Jeong , Bernard Plessier , Gary D. Hachtel , Fabio Somenzi Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jawahar Jain , Jim Bitner , Donald S. Fussell , Jacob A. Abraham Probabilistic Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Nagisa Ishiura , Hiroshi Sawada , Shuzo Yajima Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. [Citation Graph (0, 0)][DBLP ] Conf ] Seon-Woong Jeong , Bernard Plessier , Gary D. Hachtel , Fabio Somenzi Variable Ordering and Selection for FSM Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin S. Sapatnekar , Vasant B. Rao , Pravin M. Vaidya A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar Auer , Werner L. Schiele , Georg Sigl A New Linear Placement Algorithm for Cell Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Katsunori Tani , Kyoichi Izumi , Masahiko Kashimura , Tsuneo Matsuda , Takashi Fujii Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sen-Pin Lin , Charles Njinda , Melvin A. Breuer A Systematic Approach for Designing Testable VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Edwin Hsing-Mean Sha , Liang-Fang Chao Design for Easily Applying Test Vectors to Improve Delay Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Mark D. Sloan , William A. Rogers , Srihari Shoroff The Impedance Fault Model and Design for Robust Impedance Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita , Yutaka Tamiya , Yuji Kukimoto , Kuang-Chien Chen Application of Boolean Unification to Combinational Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Savoj , Robert K. Brayton , Hervé J. Touati Extracting Local Don't Cares for Network Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Savoj , Robert K. Brayton Observability Relations and Observability Don't Cares. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Cai , D. F. Wong Minimizing Channel Density by Shifting Blocks and Terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Malgorzata Marek-Sadowska , Majid Sarrafzadeh The Crossing Distribution Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Moazzem Hossain , Naveed A. Sherwani On Topological Via Minimization and Routing. [Citation Graph (0, 0)][DBLP ] Conf ] S. Miriyala , Jahangir A. Hashmi , Naveed A. Sherwani Switchbox Steiner Tree Problem in Presence of Obstacles. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaus Gouders , Reinhard Kaibel PARIS: A Parallel Pattern Fault Simulator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , Thomas M. Niermann , Janak H. Patel Methods for Reducing Events in Sequential Circuit Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyuki Takahashi , Nagisa Ishiura , Shuzo Yajima Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Terry Lee , Ibrahim N. Hajj A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita , Yusuke Matsunaga Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Improved Logic Synthesis Algorithms for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic Technology Mapping on Lookup Table-Based FPGAs for Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] 