Conferences in DBLP
Shih-Chieh Chang , Malgorzata Marek-Sadowska Perturb and simplify: multi-level boolean network optimizer. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Kunz , Premachandran R. Menon Multi-level logic optimization by implication analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Brand , Anthony D. Drumm , Sandip Kundu , Prakash Narain Incremental synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] David Karchmer , Jonathan Rose Definition and solution of the memory packing problem for field-programmable systems. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Kolson , Alexandru Nicolau , Nikil D. Dutt Integrating program transformations in the memory-based synthesis of image and video algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Florin Balasa , Francky Catthoor , Hugo De Man Dataflow-driven memory allocation for multi-dimensional signal processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Gläser , Heinrich Theodor Vierhaus , M. Kley , A. Wiederhold Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel G. Saab , Youssef Saab , Jacob A. Abraham Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. [Citation Graph (0, 0)][DBLP ] Conf ] Giri Devarayanadurg , Mani Soma Analytical fault modeling and static test generation for analog ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Honghua Yang , D. F. Wong Efficient network flow based min-cut balanced partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Wilburt Labio , Narayanan Shivakumar Multi-way VLSI circuit partitioning based on dual net representation. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Andrew B. Kahng A general framework for vertex orderings, with applications to netlist clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Gary D. Hachtel , Mariano Hermida de la Rica , Abelardo Pardo , Massimo Poncino , Fabio Somenzi Re-encoding sequential circuits to reduce power dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Mazhar Alidina , José C. Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios C. Papaefthymiou Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Ying Tsui , Massoud Pedram , Chih-Ang Chen , Alvin M. Despain Low power state assignment targeting two-and multi-level logic implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Jan M. Rabaey Algorithm selection: a quantitative computation-intensive optimization approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel , Rolf Ernst , Ulrich Holtmann , Thomas Benner Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Steven Vercauteren Synthesis of concurrent system interface modules with automatic protocol conversion generation. [Citation Graph (0, 0)][DBLP ] Conf ] Sybille Hellebrand , Hans-Joachim Wunderlich An efficient procedure for the synthesis of fast self-testable controller structures. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Gupta , Janusz Rajski , Jerzy Tyszer Test pattern generation based on arithmetic operations. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Huan Chiang , Sandeep K. Gupta Random pattern testable logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Anmol Mathur , C. L. Liu Compression-relaxation: a new approach to performance driven placement for regular architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Wern-Jieh Sun , Carl Sechen A loosely coupled parallel algorithm for standard cell placement. [Citation Graph (0, 0)][DBLP ] Conf ] Weitong Chuang , Ibrahim N. Hajj Delay and area optimization for compact placement by gate resizing and relocation. [Citation Graph (0, 0)][DBLP ] Conf ] Hannah Honghua Yang , D. F. Wong Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Masao Sato , Tatsuo Ohtsuki A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Chang Lin , Malgorzata Marek-Sadowska , Duane Gatlin Universal logic gate for FPGA design. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-Ping Juan , Viraphol Chaiyakul , Daniel D. Gajski Condition graphs for high-quality behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Claudionor José Nunes Coelho Jr. , Giovanni De Micheli Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Seong Yong Ohm , Fadi J. Kurdahi , Nikil D. Dutt Comprehensive lower bound estimation from behavioral descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Dharchoudhury , Sung-Mo Kang , K. H. (Kane) Kim , S. H. Lee Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-Lin Yu , Bryan D. Ackland VLSI timing simulation with selective dynamic regionization. [Citation Graph (0, 0)][DBLP ] Conf ] Syed A. Aftab , M. A. Styblinski A new efficient approach to statistical delay modeling of CMOS digital combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Cheng-Kok Koh Simultaneous driver and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Chung-Wen Albert Tsao Low-cost single-layer clock trees with exact zero Elmore delay skew. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo E. Téllez , Majid Sarrafzadeh Clock period constrained minimal buffer insertion in clock trees. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Richard L. Rudell Efficient implementation of retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Tolga Soyata , Eby G. Friedman Retiming with non-zero clock skew, variable register, and interconnect delay. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Grodstein , Eric Lehman , Heather Harkness , Hervé J. Touati , Bill Grundmann Optimal latch mapping and retiming within a tree. [Citation Graph (0, 0)][DBLP ] Conf ] Mark H. Linderman , Miriam Leeser Simulation of digital circuits in the presence of uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang T. Eisenmann , Helmut E. Graeb Fast transient power and noise estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer The Inversion Algorithm for digital simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Michiko Miura-Mattausch , Ute Feldmann , Alexander Rahm , Michael Bollu , Dominique Savignac Unified complete MOSFET model for analysis of digital and analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] J. R. Phillips , J. White A precorrected-FFT method for capacitance extraction of complicated 3-D structures. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Felt , Amit Narayan , Alberto L. Sangiovanni-Vincentelli Measurement and modeling of MOS transistor current mismatch in analog IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Jae Chung , Chung-Kuan Cheng Skew sensitivity minimization of buffered clock tree. [Citation Graph (0, 0)][DBLP ] Conf ] Shen Lin , C. K. Wong Process-variation-tolerant clock skew minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuho Seki , Kenji Inoue , Kazuo Kato , Kouki Tsurusaki , Shin'ichi Fukasawa , Hitoshi Sasaki , Mutsuhito Aizawa A specified delay accomplishing clock router using multiple layers. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Marculescu , Diana Marculescu , Massoud Pedram Switching activity analysis considering spatiotemporal correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Tan-Li Chou , Kaushik Roy , Sharat Prasad Estimation of circuit activity considering signal correlations and simultaneous switching. [Citation Graph (0, 0)][DBLP ] Conf ] Jiing-Yuan Lin , Tai-Chien Liu , Wen-Zen Shen A cell-based power estimation in CMOS combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Smita Bakshi , Daniel D. Gajski Design exploration for high-performance pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Ming Fang , D. F. Wong Simultaneous functional-unit binding and floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhito Ito , Lori E. Lucke , Keshab K. Parhi Module selection and data format conversion for cost-optimal DSP synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On testing delay faults in macro-based combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Jacob A. Abraham RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Yang Pan , Kwang-Ting Cheng , Sandeep Gupta A comprehensive fault macromodel for opamps. [Citation Graph (0, 0)][DBLP ] Conf ] Shigetoshi Nakatake , Yoji Kajitani Channel-driven global routing with consistent placement (extended abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Wen Chang , Shashidhar Thakur , Kai Zhu , D. F. Wong A new global routing algorithm for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Liang Wu , Douglas Chang On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. [Citation Graph (0, 0)][DBLP ] Conf ] R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi A symbolic method to reduce power consumption of circuits containing false paths. [Citation Graph (0, 0)][DBLP ] Conf ] Sasan Iman , Massoud Pedram Multi-level network optimization for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Tamiya , Yusuke Matsunaga , Masahiro Fujita LP based cell selection with constraints of timing, area, and power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Tiwari , Sharad Malik , Andrew Wolfe Power analysis of embedded software: a first step towards software power minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Ing-Jer Huang , Alvin M. Despain Generating instruction sets and microarchitectures from applications. [Citation Graph (0, 0)][DBLP ] Conf ] Clifford Liem , Trevor C. May , Pierre G. Paulin Register assignment through resource classification for ASIP microcode generation. [Citation Graph (0, 0)][DBLP ] Conf ] Roland W. Freund , Peter Feldmann Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Haifang Liao , Wayne Wei-Ming Dai Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage RC interconnect synthesis-a moment fitting approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhiro Takahashi , Kazuo Nakajima , Masayuki Terai , Koji Sato Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Venkat Thanvantri , Sartaj K. Sahni Folding a stack of equal width components. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , Weiping Shi , C. L. Liu Area minimization for hierarchical floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Pixley , Vigyan Singhal , Adnan Aziz , Robert K. Brayton Multi-level synthesis for safe replaceability. [Citation Graph (0, 0)][DBLP ] Conf ] Felice Balarin , Alberto L. Sangiovanni-Vincentelli Iterative algorithms for formal verification of embedded real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gitanjali Swamy , Robert K. Brayton Incremental formal design verification. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy M. Burks , Karem A. Sakallah Optimization of critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP ] Conf ] Michel R. C. M. Berkelaar , Pim H. W. Buurman , Jochen A. G. Jess Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. [Citation Graph (0, 0)][DBLP ] Conf ] How-Rern Lin , TingTing Hwang Dynamical identification of critical paths for iterative gate sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Salvador Mir , Vladimir Kolarik , Marcelo Lubaszewski , C. Nielsen , Bernard Courtois Built-in self-test and fault diagnosis of fully differential analogue circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Bozena Kaminska , Janusz Rzeszut A new built-in self-test approach for digital-to-analog and analog-to-digital converters. [Citation Graph (0, 0)][DBLP ] Conf ] Georges G. E. Gielen , Zhihua Wang , Willy M. C. Sansen Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter van der Wolf , K. Olav ten Bosch , Alfred van der Hoeven An enhanced flow model for constraint handling in hierarchical multi-view design environments. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Schürmann , Joachim Altmeyer , Martin Schütze On modeling top-down VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Margarida F. Jacome , Stephen W. Director A formal basis for design process planning and management. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Goossens , Ivo Bolsens , Bill Lin , Francky Catthoor Design of heterogeneous ICs for mobile and personal communication systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Schuette , John R. Barr Embedded systems design for low energy consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Srinivas Devadas Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , Bill Lin , David L. Dill , Srinivas Devadas Performance-driven synthesis of asynchronous controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Polly Siegel , Giovanni De Micheli Decomposition methods for library binding of speed-independent asynchronous designs. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On error correction in macro-based circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Boppana , W. Kent Fuchs Fault dictionary compaction by output sequence removal. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Iwashita , Satoshi Kowatari , Tsuneo Nakata , Fumiyasu Hirose Automatic test program generation for pipelined processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tamal Mukherjee , L. Richard Carley , Rob A. Rutenbar Synthesis of manufacturable analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] F. Medeiro , Francisco V. Fernández , Rafael Domínguez-Castro , Ángel Rodríguez-Vázquez A statistical optimization-based approach for automated sizing of analog cells. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Demir , Edward W. Y. Liu , Alberto L. Sangiovanni-Vincentelli Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolin Liu , Ioannis G. Tollis Improving over-the-cell channel routing in standard cell design. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Gao , C. L. Liu Minimum crosstalk switchbox routing. [Citation Graph (0, 0)][DBLP ] Conf ] Desmond Kirkpatrick , Alberto L. Sangiovanni-Vincentelli Techniques for crosstalk avoidance in the physical design of high-performance digital systems. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Matthew Cheong Efficient breadth-first manipulation of binary decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Shipra Panda , Fabio Somenzi , Bernard Plessier Symmetry detection and dynamic variable ordering of decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Kukimoto , Masahiro Fujita , Robert K. Brayton A redesign technique for combinational circuits based on gate reconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Miodrag Potkonjak Non-scan design-for-testability of RT-level data paths. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinobu Ono Selecting partial scan flip-flops for circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba , Edward J. McCluskey Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jianfeng Shao , Ramesh Harjani Macromodeling of analog circuits for hierarchical circuit design. [Citation Graph (0, 0)][DBLP ] Conf ] Qicheng Yu , Carl Sechen Approximate symbolic analysis of large analog integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Felt , Alberto L. Sangiovanni-Vincentelli Testing of analog systems using behavioral models and optimal experimental design techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Yuan Chao , D. F. Wong Layer assignment for high-performance multi-chip modules. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Liang Lin , Majid Sarrafzadeh , Chak-Kuen Wong The reproducing placement problem with applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Liang Eric Cheng RISA: accurate and efficient placement routability modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Chunduri Rama Mohan , Partha Pratim Chakrabarti A new approach for factorizing FSM's. [Citation Graph (0, 0)][DBLP ] Conf ] Ney Laert Vilar Calazans Boolean constrained encoding: a new formulation and a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Heinz-Josef Eikerling , Ralf Hunstock , Raul Camposano Optimization of hierarchical designs using partitioning and resynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Pin Kung , Chen-Shang Lin HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Dharchoudhury , Sung-Mo Kang , H. Cha , J. H. Patel Fast timing simulation of transient faults in digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Shung-Chih Chen A fast and memory-efficient diagnostic fault simulation for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Feehrer , Harry F. Jordan Timing uncertainty analysis for time-of-flight systems. [Citation Graph (0, 0)][DBLP ] Conf ] Subhrajit Bhattacharya , Sujit Dey , Franc Brglez Provably correct high-level timing analysis without path sensitization. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-fuw Lee , Donald T. Tang , C. K. Wong A timing analysis algorithm for circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh Sehgal , C. Y. Roger Chen , John M. Acken An object-oriented cell library manager. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim Altmeyer , Stefan Ohnsorge , Bernd Schürmann Reuse of design objects in CAD frameworks. [Citation Graph (0, 0)][DBLP ] Conf ] Olav Schettler , Susanne Heymann Towards support for design description languages in EDA framework. [Citation Graph (0, 0)][DBLP ] Conf ] 