Conferences in DBLP
Robert B. Jones , David L. Dill , Jerry R. Burch Efficient validity checking for processor verification. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Aagaard , Carl-Johan H. Seger The formal verification of a pipelined double-precision IEEE floating-point multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] K. J. Singh , P. A. Subrahmanyam Extracting RTL models from transistor netlists. [Citation Graph (0, 0)][DBLP ] Conf ] Taku Uchino , Fumihiro Minami , Takashi Mitsuhashi , Nobuyuki Goto Switching activity analysis using Boolean approximation method. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel , Kenneth Y. Yun , Steven M. Nowick , Pei-Chuan Yeh Estimation and bounding of energy consumption in burst-mode control circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tan-Li Chou , Kaushik Roy Statistical estimation of sequential circuit activity. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Chou , Jacob K. White Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Krauter , Lawrence T. Pileggi Generating sparse partial inductance matrices with guaranteed stability. [Citation Graph (0, 0)][DBLP ] Conf ] Ramachandra Achar , Michel S. Nakhla , Qi-Jun Zhang Addressing high frequency effects in VLSI interconnects with full wave model and CFH. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Ganguly , Shervin Hojat Clock distribution design and verification for PowerPC microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo E. Téllez , Amir H. Farrahi , Majid Sarrafzadeh Activity-driven clock design for low power circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , Chung-Wen Albert Tsao Bounded-skew clock and Steiner routing under Elmore delay. [Citation Graph (0, 0)][DBLP ] Conf ] Shipra Panda , Fabio Somenzi Who are the variables in your neighborhood. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoharu Hamaguchi , Akihito Morita , Shuzo Yajima Efficient construction of binary moment diagrams for verifying arithmetic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Brand , Reinaldo A. Bergamaschi , Leon Stok Be careful with don't cares. [Citation Graph (0, 0)][DBLP ] Conf ] Sybille Hellebrand , Birgit Reeb , Steffen Tarnick , Hans-Joachim Wunderlich Pattern generation for a deterministic BIST scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele , Hans-Joachim Wunderlich Test register insertion with minimum hardware cost. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Yang Pan , Kwang-Ting Cheng Pseudo-random testing and signature analysis for mixed-signal circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan Efficient and accurate transient simulation in charge-voltage plane. [Citation Graph (0, 0)][DBLP ] Conf ] D. Zhou , N. Chen , W. Cai A fast wavelet collocation method for high-speed VLSI circuit simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Hedrich , Erich Barke A formal approach to nonlinear analog circuit verification. [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Gupta , Lawrence T. Pileggi Constrained multivariable optimization of transmission lines with general topologies. [Citation Graph (0, 0)][DBLP ] Conf ] John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin Optimal wire sizing and buffer insertion for low power and a generalized delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Menezes , Ross Baldick , Lawrence T. Pileggi A sequential quadratic programming approach to concurrent gate and wire sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Kavita Ravi , Fabio Somenzi High-density reachability analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Masahiro Fujita , Xudong Zhao Hybrid decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Michael Kishinevsky , Luciano Lavagno , Alexandre Yakovlev Synthesizing Petri nets from state-based models. [Citation Graph (0, 0)][DBLP ] Conf ] Hussain Al-Asaad , John P. Hayes Design verification via simulation and automatic test pattern generation. [Citation Graph (0, 0)][DBLP ] Conf ] Yiming Gong , Sreejit Chakravarty On adaptive diagnostic test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Chess , David B. Lavo , F. Joel Ferguson , Tracy Larrabee Diagnosis of realistic bridging faults with single stuck-at information. [Citation Graph (0, 0)][DBLP ] Conf ] Nishath K. Verghese , David J. Allstot SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] T. Smedes , N. P. van der Meijs , A. J. van Genderen Extraction of circuit models for substrate cross-talk. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin J. Kerns , Ivan L. Wemple , Andrew T. Yang Stable and efficient reduction of substrate model networks using congruence transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Hannah Honghua Yang , D. F. Wong New algorithms for min-cut replication in partitioned circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jianmin Li , John Lillis , Chung-Kuan Cheng Linear decomposition algorithm for VLSI design applications. [Citation Graph (0, 0)][DBLP ] Conf ] Lung-Tien Liu , Ming-Ter Kuo , Shih-Chen Huang , Chung-Kuan Cheng A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant Binary decision diagrams and beyond: enabling technologies for formal verification. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence T. Pileggi Coping with RC(L) interconnect design headaches. [Citation Graph (0, 0)][DBLP ] Conf ] Michel R. C. M. Berkelaar , Lukas P. P. P. van Ginneken Efficient orthonormality testing for synthesis with pass-transistor selectors. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Lehman , Yosinori Watanabe , Joel Grodstein , Heather Harkness Logic decomposition during technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , Daniel Brand , Leon Stok , Michel R. C. M. Berkelaar , S. Prakash Efficient use of large don't cares in high-level and logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Ross B. Ortega , Gaetano Borriello Interface co-synthesis techniques for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ti-Yen Yen , Wayne Wolf Communication synthesis for distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Sujit Dey , Kazutoshi Wakabayashi Design-for-debugging of application specific designs. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Henftling , Hannes C. Wittmann , Kurt Antreich A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Srimat T. Chakradhar Acceleration techniques for dynamic vector compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Mitrajit Chatterjee , Dhiraj K. Pradhan , Wolfgang Kunz LOT: logic optimization with testability-new transformations using recursive learning. [Citation Graph (0, 0)][DBLP ] Conf ] Tanay Karnik , Sung-Mo Kang An empirical model for accurate estimation of routing delay in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sudip K. Nag , Rob A. Rutenbar Performance-driven simultaneous place and route for island-style FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Kei Mak , D. F. Wong Board-level multi-terminal net routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Chowdhary , John P. Hayes Technology mapping for field-programmable gate arrays using integer programming. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Sawada , Takayuki Suyama , Akira Nagoya Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Juinn-Dar Huang , Jing-Yang Jou , Wen-Zen Shen Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Chi Teng , Anthony M. Hill , Sung-Mo Kang Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hakan Yalcin , John P. Hayes Hierarchical timing analysis using conditional delays. [Citation Graph (0, 0)][DBLP ] Conf ] Yau-Tsun Steven Li , Sharad Malik , Andrew Wolfe Performance estimation of embedded software with instruction cache modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Sudarsanam , Sharad Malik Memory bank and register allocation in software synthesis for ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] Stan Y. Liao , Srinivas Devadas , Kurt Keutzer , Steven W. K. Tjiang Instruction selection using binate covering for code size optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Kenneth L. McMillan , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli , Patrick Scaglia Fast discrete function evaluation using decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Sharad Malik Fast functional simulation using branching programs. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Woods , Giorgio Casinovi Gate-level simulation of digital circuits using multi-valued Boolean algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Guangqiu Chen , Hidetoshi Onodera , Keikichi Tamaru An iterative gate sizing approach with accurate delay evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] R. Iris Bahar , Fabio Somenzi Boolean techniques for low power driven re-synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Sasan Iman , Massoud Pedram Two-level logic minimization for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Wing Hang Wong , Rajiv Jain PARAS: system-level concurrent partitioning and scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Wayne Wolf Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Farrahi , Majid Sarrafzadeh System partitioning to maximize sleep time. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Grodstein , Eric Lehman , Heather Harkness , Bill Grundmann , Yosinatori Watanabe A delay model for logic synthesis of continuously-sized networks. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin S. Sapatnekar , Weitong Chuang Power vs. delay in gate sizing: conflicting objectives? [Citation Graph (0, 0)][DBLP ] Conf ] Harsha Sathyamurthy , Sachin S. Sapatnekar , John P. Fishburn Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani Rectangle-packing-based module placement. [Citation Graph (0, 0)][DBLP ] Conf ] Weiping Shi An optimal algorithm for area minimization of slicing floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Anmol Mathur , K. C. Chen , C. L. Liu Re-engineering of timing constrained placements for regular architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm Power estimation techniques for integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Lippens , Vijay Nagasamy , Wayne Wolf CAD challenges in multimedia computing. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit , Donald E. Thomas Address generation for memories containing multiple arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gjalt G. de Jong , Bill Lin , Carl Verdonck , Sven Wuytack , Francky Catthoor Background memory management for dynamic data structure intensive processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhao , Christos A. Papachristou Architectural partitioning of control memory for application specific programmable processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Chang Lin , Mike Tien-Chien Lee , Malgorzata Marek-Sadowska , Kuang-Chien Chen Cost-free scan: a low-overhead scan path design methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Vijay Gangaram , Miodrag Potkonjak A controller-based design-for-testability technique for controller-data path circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer On testable multipliers for fixed-width data path architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Crols , Stéphane Donnay , Michiel Steyaert , Georges G. E. Gielen A high-level design and optimization tool for analog RF receiver front-ends. [Citation Graph (0, 0)][DBLP ] Conf ] S. R. Kadivar , Doris Schmitt-Landsiedel , H. Klar A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo J. Peralías , Adoración Rueda , José Luis Huertas Statistical behavioral modeling and characterization of A/D converters. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Lei He Optimal wiresizing for interconnects with multiple sources. [Citation Graph (0, 0)][DBLP ] Conf ] Tianxiong Xue , Ernest S. Kuh Post routing performance optimization via multi-link insertion and non-uniform wiresizing. [Citation Graph (0, 0)][DBLP ] Conf ] Man-Fai Yu , Wayne Wei-Ming Dai Single-layer fanout routing and routability analysis for Ball Grid Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Nelson L. Passos , Edwin Hsing-Mean Sha Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications. [Citation Graph (0, 0)][DBLP ] Conf ] Fermín Sánchez Time-Constrained Loop Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Niraj K. Jha An iterative improvement algorithm for low power data path synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Fuhrer , Bill Lin , Steven M. Nowick Symbolic hazard-free minimization and encoding of asynchronous finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan Aziz , Felice Balarin , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP ] Conf ] Walter M. Lindermeir , Helmut E. Graeb , Kurt Antreich Design based analog testing by Characteristic Observation Inference. [Citation Graph (0, 0)][DBLP ] Conf ] Giri Devarayanadurg , Mani Soma Dynamic test signal design for analog ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Shenshung Chiang , Shyh-Jye Jou Impulse response fault model and fault extraction for functional level analog circuit diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Hirendu Vaishnav , Massoud Pedram Delay optimal partitioning targeting low power VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Kuznar , Franc Brglez PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. [Citation Graph (0, 0)][DBLP ] Conf ] David Ihsin Cheng , Chih-Chang Lin , Malgorzata Marek-Sadowska Circuit partitioning with logic perturbation. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Iyer , Ramesh Karri , Israel Koren Phantom redundancy: a high-level synthesis approach for manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Elof Frank , Thomas Lengauer APPlaUSE: Area and performance optimization in a unified placement and synthesis environment. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Sunil D. Sherlekar , G. Venkatesh Synthesis of multiplier-less FIR filters with minimum number of additions. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Dahlgren A multiple-dominance switch-level model for simulation of short faults. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Shi-Yu Huang , Wei-Jin Dai Fault emulation: a new approach to fault grading. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Functional test generation for delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kannan Krishna , Stephen W. Director A novel methodology for statistical parameter extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Boris Troyanovsky , Zhiping Yu , Lydia So , Robert W. Dutton Relaxation-based harmonic balance technique for semiconductor device simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Haifang Liao , Wayne Wei-Ming Dai Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathi Dasgupta , Susmita Sur-Kolay , Bhargab B. Bhattacharya A unified approach to topology generation and area optimization of general floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Kim , Sung-Mo Kang A timing-driven data path layout synthesis with integer programming. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Yuan Chao , D. F. Wong Signal integrity optimization on the pad assignment for high-speed VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Huey-Yih Wang , Robert K. Brayton Multi-level logic optimization of FSM networks. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna P. Belkhale , Alexander J. Suess Timing analysis with known false sub graphs. [Citation Graph (0, 0)][DBLP ] Conf ] 