Conferences in DBLP
Xin Li , Jiayong Le , Padmini Gopalakrishnan , Lawrence T. Pileggi Asymptotic probability extraction for non-normal distributions of circuit performance. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Hamid Mahmoodi-Meimand , Kaushik Roy Statistical design and optimization of SRAM cell for yield enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , Hai Zhou Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Jinfeng Liu , Pai H. Chou Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kihwan Choi , Wonbok Lee , Ramakrishna Soma , Massoud Pedram Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Dakai Zhu , Rami G. Melhem , Daniel Mossé The effects of energy management on reliability in real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Per Bjesse , Arne Borälv DAG-aware circuit compression for formal verification. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kuehlmann Dynamic transition relation simplification for bounded property checking. [Citation Graph (0, 0)][DBLP ] Conf ] Zurab Khasidashvili , Marcelo Skaba , Daher Kaiss , Ziyad Hanna Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Kroening , Edmund M. Clarke Checking consistency of C and Verilog using predicate abstraction and induction. [Citation Graph (0, 0)][DBLP ] Conf ] Yangfeng Su , Jian Wang , Xuan Zeng , Zhaojun Bai , Charles Chiang , Dian Zhou SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Roland W. Freund SPRIM: structure-preserving reduced-order interconnect macromodeling. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , F. Liu Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Jitesh Jain , Cheng-Kok Koh , Venkataramanan Balakrishnan Fast simulation of VLSI interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Quming Zhou , Kartik Mohanram Cost-effective radiation hardening technique for combinational logic. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Srinivasan , Aman Gayasen , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Yuan Xie , Mary Jane Irwin Improving soft-error tolerance of FPGA configuration bits. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Zhang , Naresh R. Shanbhag A soft error rate analysis (SERA) methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Mary Jane Irwin , Guilin Chen , Ibrahim Kolcu Banked scratch-pad memory management for reducing leakage energy consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Kimish Patel , Enrico Macii , Luca Benini , Massimo Poncino Reducing cache misses by application-specific re-configurable indexing. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Poncino , Jianwen Zhu DynamoSim: a trace-based dynamically compiled instruction set simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Sani R. Nassif , Duane S. Boning , Nagib Hakim The care and feeding of your statistical static timer. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Kasnavi , Joddy W. Wang , Mahmoud Shahram , Jindrich Zejda Analytical modeling of crosstalk noise waveforms using Weibull function. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Keller , Ken Tseng , Nishath K. Verghese A robust cell-level crosstalk delay change analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiming Chen , Hai Zhou Timing macro-modeling of IP blocks with crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Alexey Glebov , Sergey Gavrilov , R. Soloviev , Vladimir Zolotov , Murat R. Becer , Chanhee Oh , Rajendran Panda Delay noise pessimism reduction by logic correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Hosangadi , Farzan Fallah , Ryan Kastner Factoring and eliminating common subexpressions in polynomial expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Püschel , A. C. Zelinski , James C. Hoe Custom-optimized multiplierless implementations of DSP algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Newton Cheung , Sri Parameswaran , Jörg Henkel A quantitative study and estimation models for extensible instructions in embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] André C. Nácul , Tony Givargis Code partitioning for synthesis of embedded applications with phantom. [Citation Graph (0, 0)][DBLP ] Conf ] Sayantan Das , Prasenjit Basu , Ansuman Banerjee , Pallab Dasgupta , P. P. Chakrabarti , Chunduri Rama Mohan , Limor Fix , Roy Armoni Formal verification coverage: computing the coverage gap between temporal specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Moayad Fahim Ali , Andreas G. Veneris , Alexander Smith , Sean Safarpour , Rolf Drechsler , Magdy S. Abadir Debugging sequential circuits using Boolean satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Smriti Gupta , Bruce H. Krogh , Rob A. Rutenbar Towards formal verification of analog designs. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Il Kim , Chong-Min Kyung Automatic translation of behavioral testbench for fully accelerated simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Su , Krishnendu Chakrabarty Architectural-level synthesis of digital microfluidics-based biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Anton J. Pfeiffer , Tamal Mukherjee , Steinar Hauan Simultaneous design and placement of multiplexed chemical processing systems on microchips. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Raychowdhury , Kaushik Roy A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Li , Narayan R. Aluru Hybrid techniques for electrostatic analysis of nanowires. [Citation Graph (0, 0)][DBLP ] Conf ] Yehea I. Ismail , Chirayu S. Amin Computation of signal threshold crossing times directly from higher order moments. [Citation Graph (0, 0)][DBLP ] Conf ] Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail Modeling unbuffered latches for timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Omedes , Michel Robert , Mohammed Ramdani A flexibility aware budgeting for hierarchical flow timing closure. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Energy optimization for a two-device data flow chain. [Citation Graph (0, 0)][DBLP ] Conf ] Vikas Chandra , Herman Schmit , Anthony Xu , Lawrence T. Pileggi A power aware system level interconnect design methodology for latency-insensitive systems. [Citation Graph (0, 0)][DBLP ] Conf ] V. Seth , Min Zhao , Jiang Hu Exploiting level sensitive latches in wire pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Cheng , Martin D. F. Wong Floorplan design for multi-million gate FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang Temporal floorplanning using the T-tree formulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Jie Wei , Yan Zhang A thermal-driven floorplanning algorithm for 3D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Haifeng Qian , Joseph N. Kozhaya , Sani R. Nassif , Sachin S. Sapatnekar A chip-level electrostatic discharge simulation strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li , Lawrence T. Pileggi , Mehdi Asheghi , Rajit Chandra Efficient full-chip thermal modeling and analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijian Lu , Wei Huang , John Lach , Mircea R. Stan , Kevin Skadron Interconnect lifetime prediction under dynamic stress for reliability-aware design. [Citation Graph (0, 0)][DBLP ] Conf ] Paul S. Zuchowski , P. A. Habitz , J. D. Hayes , J. H. Oppold Process and environmental variation impacts on ASIC timing. [Citation Graph (0, 0)][DBLP ] Conf ] S. B. Samaan The impact of device parameter variations on the frequency and performance of VLSI chips. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond A. Heald , Ping Wang Variability in sub-100nm SRAM designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jingcao Hu , Radu Marculescu Application-specific buffer space allocation for networks-on-chip router design. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandru Andrei , Marcus T. Schmitz , Petru Eles , Zebo Peng , Bashir M. Al-Hashimi Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andhi Janapsatya , Sri Parameswaran , Aleksandar Ignjatovic Hardware/software managed scratchpad memory for embedded system. [Citation Graph (0, 0)][DBLP ] Conf ] Aaron P. Hurst , Philip Chong , Andreas Kuehlmann Physical placement driven by sequential timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Devang Jariwala , John Lillis On interactions between routing and detailed placement. [Citation Graph (0, 0)][DBLP ] Conf ] Chen Li 0004 , Min Xie , Cheng-Kok Koh , Jason Cong , Patrick H. Madden Routability-driven placement and white space allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Haoxing Ren , David Zhigang Pan , Paul Villarrubia True crosstalk aware incremental placement with noise map. [Citation Graph (0, 0)][DBLP ] Conf ] Jie-Hong Roland Jiang , Alan Mishchenko , Robert K. Brayton On breakable cyclic definitions. [Citation Graph (0, 0)][DBLP ] Conf ] Shrirang K. Karandikar , Sachin S. Sapatnekar Logical effort based technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava Variability inspired implementation selection problem. [Citation Graph (0, 0)][DBLP ] Conf ] Seraj Ahmad , Rabi N. Mahapatra M-trie: an efficient approach to on-chip logic minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant , Sriram K. Rajamani Verifying properties of hardware and software by predicate abstraction and model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Frederic Worm , Paolo Ienne , Patrick Thiran Soft self-synchronising codes for self-calibrating communication. [Citation Graph (0, 0)][DBLP ] Conf ] Kangmin Lee , Se-Joong Lee , Hoi-Jun Yoo SILENT: serialized low energy transmission coding for on-chip interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan Lin , Hai Zhou Optimal wire retiming without binary search. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Ma , Rob A. Rutenbar Interval-valued reduced order statistical interconnect modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , Li-C. Wang , Kwang-Ting Cheng , Sandip Kundu Static statistical timing analysis for latch-based pipeline designs. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Khandelwal , Azadeh Davoodi , Ankur Srivastava Efficient statistical timing analysis through error budgeting. [Citation Graph (0, 0)][DBLP ] Conf ] Nestoras E. Evmorfopoulos , Dimitris P. Karampatzakis , Georgios I. Stamoulis Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates. [Citation Graph (0, 0)][DBLP ] Conf ] Eli Chiprout Fast flip-chip power grid analysis via locality and grid shells. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Hao Chen , Jeng-Liang Tsai , Tanay Karnik HiSIM: hierarchical interconnect-centric circuit simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Durairaj , Priyank Kalla Guiding CNF-SAT search via efficient constraint partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Zhang , Mukul R. Prasad , Michael S. Hsiao Incremental deductive & inductive reasoning for SAT-based bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Malay K. Ganai , Aarti Gupta , Pranav Ashar Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. [Citation Graph (0, 0)][DBLP ] Conf ] Bing Li , Fabio Somenzi Efficient computation of small abstraction refinements. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Gao , John P. Hayes Exact and heuristic approaches to input vector control for leakage power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Khandelwal , Ankur Srivastava Leakage control through fine-grained placement and sizing of sleep transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Tao Hsieh , Jian-Cheng Lin , Shih-Chieh Chang A vectorless estimation of maximum instantaneous current for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Satrajit Chatterjee , Robert K. Brayton A new incremental placement algorithm and its application to congestion-aware divisor extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh N. Adya , S. Chaturvedi , Jarrod A. Roy , David A. Papa , Igor L. Markov Unification of partitioning, placement and floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Malgorzata Marek-Sadowska Multilevel expansion-based VLSI placement with blockages. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Qinke Wang An analytic placer for mixed-size placement and timing-driven placement. [Citation Graph (0, 0)][DBLP ] Conf ] Kristofer Vorwerk , Andrew A. Kennings , Anthony Vannelli Engineering details of a stable force-directed placer. [Citation Graph (0, 0)][DBLP ] Conf ] Yajun Ran , Malgorzata Marek-Sadowska An integrated design flow for a via-configurable gate array. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Jayakumar , Sunil P. Khatri A metal and via maskset programmable VLSI design methodology using PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Renqiu Huang , Ranga Vemuri Analysis and evaluation of a hybrid interconnect structure for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Helge Anderson , Farid N. Najm Low-power programmable routing circuitry for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Liang Tsai , Dong Hyun Baik , Charlie Chung-Ping Chen , Kewal K. Saluja A yield improvement methodology using pre- and post-silicon statistical clock scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiming Chen , Hai Zhou Clock schedule verification under process variations. [Citation Graph (0, 0)][DBLP ] Conf ] A. Kapoor , Nikhil Jayakumar , Sunil P. Khatri A novel clock distribution and dynamic de-skewing methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Tokiharu Miyoshi , Seiji Kajihara , Laung-Terng Wang , Kewal K. Saluja , Kozo Kinoshita On per-test fault diagnosis using the X-fault model. [Citation Graph (0, 0)][DBLP ] Conf ] Fang Liu , Sule Ozev , Martin A. Brooke Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu An efficient method for improving the quality of per-test fault diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Soheil Ghiasi , Elaheh Bozorgzadeh , Siddharth Choudhuri , Majid Sarrafzadeh A unified theory of timing budget management. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Wu , Jianwen Zhu , Farid N. Najm Dynamic range estimation for nonlinear systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Zhong , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Power estimation for cycle-accurate functional descriptions of hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li , Lawrence T. Pileggi Efficient harmonic balance simulation using multi-level frequency decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaochun Duan , Kartikeya Mayaram Frequency domain simulation of high-Q oscillators with homotopy methods. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolue Lai , Jaijeet S. Roychowdhury Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking. [Citation Graph (0, 0)][DBLP ] Conf ] C. Chu FLUTE: fast lookup table based wirelength estimation technique. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer L. Wong , Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava , Miodrag Potkonjak Wire-length prediction using statistical techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Jiang Hu , Sachin S. Sapatnekar , Cliff C. N. Sze Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP ] Conf ] Leonard Lee , Li-C. Wang , T. M. Mak , Kwang-Ting Cheng A path-based methodology for post-silicon timing validation. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjing Rao , Alex Orailoglu , G. Su Frugal linear network-based test decompression for drastic test cost reductions. [Citation Graph (0, 0)][DBLP ] Conf ] Baris Arslan , Alex Orailoglu Design space exploration for aggressive test cost reduction in CircularScan architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Koenemann Design/process learning from electrical test. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Lavin , Fook-Luen Heng , Gregory A. Northrop Backend CAD flows for "restrictive design rules". [Citation Graph (0, 0)][DBLP ] Conf ] Maxim Teslenko , Elena Dubrova Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth. [Citation Graph (0, 0)][DBLP ] Conf ] Deming Chen , Jason Cong DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Li , Yan Lin , Lei He Vdd programmability to reduce FPGA interconnect power. [Citation Graph (0, 0)][DBLP ] Conf ] Lei He , Tulika Mitra , Weng-Fai Wong Configuration bitstream compression for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind , Rishiyur S. Nikhil , Daniel L. Rosenband , Nirav Dave High-level synthesis: an essential ingredient for designing complex ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Chao Huang , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha High-level synthesis using computation-unit integrated memories. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay K. Verma , Paolo Ienne Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Maged Ghoneima , Yehea I. Ismail Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Srivastava , Dennis Sylvester A general framework for probabilistic low-power design space exploration considering process variation. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Junji Yamaguchi , Hidetoshi Onodera Timing analysis considering spatial power/ground level variation. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong Simultaneous escape routing and layer assignment for dense PCBs. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong A provably good algorithm for high performance bus routing. [Citation Graph (0, 0)][DBLP ] Conf ] R. Fung , V. Betz , W. Chow Simultaneous short-path and long-path timing optimization for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Stehr , Helmut E. Graeb , Kurt Antreich Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Padmini Gopalakrishnan , Yang Xu , Lawrence T. Pileggi Robust analog/RF circuit design with projection-based posynomial modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Jintae Kim , Jaeseo Lee , Lieven Vandenberghe Techniques for improving the accuracy of geometric-programming based analog circuit design optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Joel R. Phillips Variational interconnect analysis via PMTBR. [Citation Graph (0, 0)][DBLP ] Conf ] Janet Meiling Wang , Praveen Ghanta , Sarma B. K. Vrudhula Stochastic analysis of interconnect performance in the presence of process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenhai Zhu , Jacob White , Alper Demir A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Daisuke Maruyama , Akira Kanuma , Takashi Mochiyama , Hiroaki Komatsu , Yaroku Sugiyama , Noriyuki Ito Detection of multiple transitions in delay fault test of SPARC64 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Chmelar Minimizing the number of test configurations for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Shi , Yiorgos Makris SPIN-TEST: automatic test pattern generation for speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] A. Bernstein , M. Burton , Frank Ghenassia How to bridge the abstraction gap in system level modeling and design. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Ghenassia , Narayanan Vijaykrishnan , Mary Jane Irwin Analyzing software influences on substrate noise: an ADC perspective. [Citation Graph (0, 0)][DBLP ] Conf ] F. De Bernarclinis , S. Gambini , R. Vincis , F. Svelto Design space exploration for a UMTS front-end exploiting analog platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Ranga Vemuri , Glenn Wolfe Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. [Citation Graph (0, 0)][DBLP ] Conf ] 