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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
1999 (conf/iccad/1999)

  1. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    Marsh: min-area retiming with setup and hold constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:2-6 [Conf]
  2. Robert M. Fuhrer, Steven M. Nowick
    OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:7-13 [Conf]
  3. Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.
    Bit-level arithmetic optimization for carry-save additions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:14-19 [Conf]
  4. Hussein Etawil, Shawki Areibi, Anthony Vannelli
    Attractor-repeller approach for global placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:20-24 [Conf]
  5. Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz
    Cell replication and redundancy elimination during placement for cycle time optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:25-30 [Conf]
  6. Jinan Lou, Wei Chen, Massoud Pedram
    Concurrent logic restructuring and placement for timing closure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:31-36 [Conf]
  7. Aiguo Xie, Peter A. Beerel
    Implicit enumeration of strongly connected components. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:37-40 [Conf]
  8. In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi
    Least fixpoint approximations for reachability analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:41-44 [Conf]
  9. Hiroyuki Higuchi, Fabio Somenzi
    Lazy group sifting for efficient symbolic state traversal of FSMs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:45-49 [Conf]
  10. Wolfgang Günther, Rolf Drechsler
    Efficient manipulation algorithms for linearly transformed BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:50-54 [Conf]
  11. Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli
    Noise analysis of non-autonomous radio frequency circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:55-60 [Conf]
  12. Mark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov
    New methods for speeding up computation of Newton updates in harmonic balance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:61-64 [Conf]
  13. Maria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee
    Design and optimization of LC oscillators. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:65-69 [Conf]
  14. Alper Demir, Peter Feldmann
    Modeling and simulation of the interference due to digital switching in mixed-signal ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:70-75 [Conf]
  15. Chunhong Chen, Majid Sarrafzadeh
    Provably good algorithm for low power consumption with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:76-79 [Conf]
  16. Khurram Muhammad, Kaushik Roy
    A novel design methodology for high performance and low power digital filters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:80-83 [Conf]
  17. Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang
    A bipartition-codec architecture to reduce power in pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:84-90 [Conf]
  18. Tatjana Serdar, Carl Sechen
    AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:91-97 [Conf]
  19. Serkan Askar, Maciej J. Ciesielski
    Analytical approach to custom datapath design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:98-101 [Conf]
  20. Yanbin Jiang, Sachin S. Sapatnekar
    An integrated algorithm for combined placement and libraryless technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:102-106 [Conf]
  21. Min Zhao, Sachin S. Sapatnekar
    Timing-driven partitioning for two-phase domino and mixed static/domino implementations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:107-110 [Conf]
  22. Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
    Implication graph based domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:111-114 [Conf]
  23. Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu
    Synthesis for multiple input wires replacement of a gate for wiring consideration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:115-119 [Conf]
  24. Tuyen V. Nguyen, Peter O'Brien, David W. Winston
    Transient sensitivity computation for transistor level analysis and tuning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:120-123 [Conf]
  25. Yi-Kan Cheng, Sung-Mo Kang
    An efficient method for hot-spot identification in ULSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:124-127 [Conf]
  26. Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
    A scalable substrate noise coupling model for mixed-signal ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:128-131 [Conf]
  27. Pinhong Chen, Kurt Keutzer
    Towards true crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:132-138 [Conf]
  28. Paul Tafertshofer, Andreas Ganz
    SAT based ATPG using fast justification and propagation in the implication graph. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:139-146 [Conf]
  29. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    Techniques for improving the efficiency of sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:147-151 [Conf]
  30. Fatih Kocan, Daniel G. Saab
    Concurrent D-algorithm on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:152-156 [Conf]
  31. Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley
    A new heuristic for rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:157-162 [Conf]
  32. Jason Cong, Jie Fang, Kei-Yong Khoo
    An implicit connection graph maze routing algorithm for ECO routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:163-167 [Conf]
  33. Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky
    The associative-skew clock routing problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:168-172 [Conf]
  34. Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger
    Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:173-177 [Conf]
  35. David S. Kung, Ruchir Puri
    Optimal P/N width ratio selection for standard cell libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:178-184 [Conf]
  36. Rajeev Murgai
    Performance optimization under rise and fall parameters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:185-190 [Conf]
  37. Yutaka Tamiya
    Performance optimization using separator sets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:191-194 [Conf]
  38. Martin Charles Golumbic, Aviad Mintz
    Factoring logic functions using graph partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:195-199 [Conf]
  39. Bernard N. Sheehan
    TICER: realizable reduction of extracted RC circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:200-203 [Conf]
  40. Anirudh Devgan, Peter R. O'Brien
    Realizable reduction for RC interconnect circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:204-207 [Conf]
  41. Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
    RLC interconnect delay estimation via moments of amplitude and phase response. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:208-213 [Conf]
  42. Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
    Practical considerations for passive reduction of RLC circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:214-220 [Conf]
  43. Ellen Sentovich, David L. Dill, Serdar Tasiran
    Formal verification meets simulation (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:221- [Conf]
  44. Mattan Kamon, Steve McCormick, Ken Sheperd
    Interconnect parasitic extraction in the digital IC design methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:223-231 [Conf]
  45. Christoph Albrecht, Bernhard Korte, Jürgen Schietke, Jens Vygen
    Cycle time and slack optimization for VLSI-chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:232-238 [Conf]
  46. Ivan S. Kourtev, Eby G. Friedman
    Clock skew scheduling for improved reliability via quadratic programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:239-243 [Conf]
  47. Chandramouli Visweswariah, Andrew R. Conn
    Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:244-252 [Conf]
  48. Rainer Leupers, Peter Marwedel
    Function inlining under code size constraints for embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:253-256 [Conf]
  49. Daniel Benyamin, William H. Mangione-Smith
    Function unit specialization through code analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:257-260 [Conf]
  50. Margarida F. Jacome, Gustavo de Veciana
    Lower bound on latency for VLIW ASIP datapaths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:261-269 [Conf]
  51. Tony Givargis, Jörg Henkel, Frank Vahid
    Interface and cache power exploration for core-based embedded system design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:270-273 [Conf]
  52. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Dynamic power management using adaptive learning tree. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:274-279 [Conf]
  53. Giuseppe Bernacchia, Marios C. Papaefthymiou
    Analytical macromodeling for high-level power estimation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:280-283 [Conf]
  54. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino
    Parameterized RTL power models for combinational soft macros. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:284-288 [Conf]
  55. Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
    Validation and test generation for oscillatory noise in VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:289-296 [Conf]
  56. Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao
    Fault modeling and simulation for crosstalk in system-on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:297-303 [Conf]
  57. Alfred V. Gomes, Abhijit Chatterjee
    Robust optimization based backtrace method for analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:304-308 [Conf]
  58. Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
    A methodology for correct-by-construction latency insensitive design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:309-315 [Conf]
  59. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev
    What is the cost of delay insensitivity? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:316-323 [Conf]
  60. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
    Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:324-331 [Conf]
  61. Sung Tae Jung, Chris J. Myers
    Direct synthesis of timed asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:332-338 [Conf]
  62. David L. Rhodes, Wayne Wolf
    Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:339-342 [Conf]
  63. Gang Qu, Miodrag Potkonjak
    Power minimization using system-level partitioning of applications with quality of service requirements. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:343-346 [Conf]
  64. Felice Balarin
    Worst-case analysis of discrete systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:347-353 [Conf]
  65. Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning and interconnect planning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:354-357 [Conf]
  66. Jason Cong, Tianming Kong, David Zhigang Pan
    Buffer block planning for interconnect-driven floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:358-363 [Conf]
  67. Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
    A clustering- and probability-based approach for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:364-369 [Conf]
  68. Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu
    The Chebyshev expansion based passive model for distributed interconnect networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:370-375 [Conf]
  69. Emad Gad, Michel S. Nakhla
    Model reduction for DC solution of large nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:376-379 [Conf]
  70. Jing-Rebecca Li, Jacob White
    Efficient model reduction of interconnect via approximate system gramians. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:380-384 [Conf]
  71. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    A framework for testing core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:385-390 [Conf]
  72. Krishnendu Chakrabarty
    Test scheduling for core-based systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:391-394 [Conf]
  73. Qiushuang Zhang, Ian G. Harris
    Partial BIST insertion to eliminate data correlation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:395-399 [Conf]
  74. Huiqun Liu, D. F. Wong
    A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:400-405 [Conf]
  75. Inki Hong, Miodrag Potkonjak, Lisa Guerra
    Throughput optimization of general non-linear computations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:406-409 [Conf]
  76. Junhyung Um, Taewhan Kim, C. L. Liu
    Optimal allocation of carry-save-adders in arithmetic optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:410-413 [Conf]
  77. Soha Hassoun, Carolyn McCreary
    Regularity extraction via clan-based structural circuit decomposition. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:414-419 [Conf]
  78. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Repeater insertion in tree structured inductive interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:420-424 [Conf]
  79. Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
    Interconnect scaling implications for CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:425-429 [Conf]
  80. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Is wire tapering worthwhile? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:430-436 [Conf]
  81. Michael W. Beattie, Lawrence T. Pileggi
    Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:437-444 [Conf]
  82. A. J. Dammers, N. P. van der Meijs
    Virtual screening: a step towards a sparse partial inductance matrix. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:445-452 [Conf]
  83. Junfeng Wang, Johannes Tausch, Jacob K. White
    A wide frequency range surface integral formulation for 3-D RLC extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:453-458 [Conf]
  84. Sani R. Nassif, Tuyen V. Nguyen
    SOI technology and tools (abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:459- [Conf]
  85. Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar
    System level design and debug of high-performance embedded media systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:461- [Conf]
  86. Irith Pomeranz, Sudhakar M. Reddy
    An approach for improving the levels of compaction achieved by vector omission. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:463-466 [Conf]
  87. Bapiraju Vinnakota
    Deep submicron defect detection with the energy consumption ratio. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:467-470 [Conf]
  88. Pankaj Pant, Abhijit Chatterjee
    Efficient diagnosis of path delay faults in digital logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:471-476 [Conf]
  89. Preeti Ranjan Panda
    Memory bank customization and assignment in behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:477-481 [Conf]
  90. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:482-488 [Conf]
  91. Dirk Herrmann, Rolf Ernst
    Improved interconnect sharing by identity operation insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:489-493 [Conf]
  92. Thomas A. Henzinger, Xiaojun Liu, Shaz Qadeer, Sriram K. Rajamani
    Formal specification and verification of a dataflow processor array. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:494-499 [Conf]
  93. Dragos Lungeanu, C.-J. Richard Shi
    Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:500-504 [Conf]
  94. Harry Hsieh, Felice Balarin
    Synchronous equivalence for embedded systems: a tool for design exploration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:505-510 [Conf]
  95. Rajeev Murgai
    On the global fanout optimization problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:511-515 [Conf]
  96. Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj
    LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:516-519 [Conf]
  97. Jie-Hong Roland Jiang, Iris Hui-Ru Jiang
    Optimum loading dispersion for high-speed tree-type decision circuitry. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:520-525 [Conf]
  98. Clayton B. McDonald, Randal E. Bryant
    Symbolic functional and timing verification of transistor-level circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:526-530 [Conf]
  99. Kenneth L. Shepard, Dae-Jin Kim
    Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:531-538 [Conf]
  100. Alexander Saldanha
    Functional timing optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:539-543 [Conf]
  101. Yuji Kukimoto, Robert K. Brayton
    Timing-safe false path removal for combinational modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:544-550 [Conf]
  102. Rachid Helaihel, Kunle Olukotun
    JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:551-557 [Conf]
  103. Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState - an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:558-565 [Conf]
  104. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast performance analysis of bus-based system-on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:566-573 [Conf]
  105. Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton
    Probabilistic state space search. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:574-579 [Conf]
  106. Jules P. Bergmann, Mark Horowitz
    Improving coverage analysis and test generation for large designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:580-583 [Conf]
  107. Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
    Modeling design constraints and biasing in simulation using BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:584-590 [Conf]
  108. Edoardo Charbon, Ilhami Torunoglu
    Copyright protection of designs based on multi source IPs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:591-595 [Conf]
  109. Darko Kirovski, Miodrag Potkonjak
    Localized watermarking: methodology and application to operation scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:596-599 [Conf]
  110. Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong
    Copy detection for intellectual property protection of VLSI designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:600-605 [Conf]
  111. Jacob White, Gary K. Fedder, Tamal Mukherjee
    Path toward future CAD environments for MEMS (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:606- [Conf]
  112. Nikil D. Dutt, Eric Foster
    Design of a set-top box system on a chip (abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:608- [Conf]
  113. Nikil D. Dutt, Brian Kelley
    On the rapid prototyping and design of a wireless communication system on a chip (abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:609- [Conf]
  114. Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong
    Advances in transistor timing, simulation, and optimization (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:611- [Conf]
  115. Reinaldo A. Bergamaschi, Brian M. Barry, John Duimovich
    Embedded Java: techniques and applications (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:613- [Conf]
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