Conferences in DBLP
Wenrui Gong , Gang Wang , Ryan Kastner Storage assignment during high-level synthesis for configurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Ruiz-Sautua , María C. Molina , Jose Manuel Mendias , Román Hermida Performance-driven read-after-write dependencies softening in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo F. Flores , José C. Monteiro , Eduardo A. C. da Costa An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. [Citation Graph (0, 0)][DBLP ] Conf ] Ho-Yan Wong , Lerong Cheng , Yan Lin , Lei He FPGA device and architecture evaluation considering process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Yajun Ran , Malgorzata Marek-Sadowska Via-configurable routing architectures and fast design mappability estimation for regular fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Kwok-Shing Leung SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Luo , Haoxing Ren , Charles J. Alpert , David Zhigang Pan Computational geometry based placement migration. [Citation Graph (0, 0)][DBLP ] Conf ] Min Pan , Natarajan Viswanathan , Chris C. N. Chu An efficient and effective detailed placement algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Hui Chang , Igor L. Markov , Valeria Bertacco Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Hao , Forrest Brewer Wirelength optimization by optimal block orientation. [Citation Graph (0, 0)][DBLP ] Conf ] Erkan Acar , Sule Ozev Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions. [Citation Graph (0, 0)][DBLP ] Conf ] Mango Chia-Tso Chao , Seongmoon Wang , Srimat T. Chakradhar , Kwang-Ting Cheng Response shaper: a novel technique to enhance unknown tolerance for output response compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Anuja Sehgal , Krishnendu Chakrabarty Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty , J. E. Chen A cocktail approach on random access scan toward low power and high efficiency test. [Citation Graph (0, 0)][DBLP ] Conf ] David Bordoley , Hieu Nguyen , Mani Soma A statistical study of the effectiveness of BIST jitter measurement techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Osamu Takahashi , Russ Cook , Scott R. Cottier , Sang H. Dhong , Brian K. Flachs , Koji Hirairi , Atsushi Kawasumi , Hiroaki Murakami , Hiromi Noro , Hwa-Joon Oh , S. Onish , Juergen Pille , Joel Silberman The circuit design of the synergistic processor element of a CELL processor. [Citation Graph (0, 0)][DBLP ] Conf ] Richard McGowen Adaptive designs for power and thermal optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Staszewski , Khurram Muhammad , Dirk Leipold Digital RF processor (DRP/spl trade/) for cellular phones. [Citation Graph (0, 0)][DBLP ] Conf ] Jianfeng Luo , Qing Su , Charles Chiang , Jamil Kawa A layout dependent full-chip copper electroplating topography model. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Ma , Claire Fang Fang , Rob A. Rutenbar , Xiaolin Xie , Duane S. Boning Interval-valued statistical modeling of oxide chemical-mechanical polishing. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Chiang , Andrew B. Kahng , Subarna Sinha , Xu Xu Fast and efficient phase conflict detection and correction in standard-cell layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Chieh Chen , Yao-Wen Chang , Shyh-Chang Lin IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Michail Romesis , Joseph R. Shinnerl Robust mixed-size placement under tight white-space constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sherief Reda Intrinsic shortest path length: a new, accurate a priori wirelength estimator. [Citation Graph (0, 0)][DBLP ] Conf ] Yinghua Li , Alex Kondratyev , Robert K. Brayton Synthesis methodology for built-in at-speed testing. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan Lin , Jia Wang , Hai Zhou Clustering for processing rate optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sanghamitra Roy , Weijen Chen ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Tsu-Jae King FinFETs for nanoscale CMOS digital integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal P. Trivedi , Jerry G. Fossum , Leo Mathew , Murshed M. Chowdhury , Weimin Zhang , Glenn O. Workman , Bich-Yen Nguyen Physics-based compact modeling for nonclassical CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Hamid Mahmoodi-Meimand , Saibal Mukhopadhyay , Hari Ananthan , Aditya Bansal , Tamer Cakici Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy A. Rowlette , Eric Pop , Sanjiv Sinha , Mathew Panzer , Kenneth E. Goodson Thermal simulation techniques for nanoscale transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Karam S. Chatha , Goran Konjevod An automated technique for topology and route generation of application specific on-chip interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Martin K. F. Schafer , Thomas Hollstein , Heiko Zimmer , Manfred Glesner Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Ümit Y. Ogras , Radu Marculescu Application-specific network-on-chip architecture customization via long-range link insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Chan , Sri Parameswaran NoCEE: energy macro-model extraction methodology for network on chip routers. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Guoling Han , Zhiru Zhang Architecture and compilation for data bandwidth improvement in configurable embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Mahmut T. Kandemir Code restructuring for improving cache performance of MPSoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir 2D data locality: definition, abstraction, and application. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Ozcan Ozturk , Mahmut T. Kandemir , Ibrahim Kolcu Integrating loop and data optimizations for locality within a constraint network based framework. [Citation Graph (0, 0)][DBLP ] Conf ] Tarvo Raudvere , Ashish Kumar Singh , Ingo Sander , Axel Jantsch System level verification of digital signal processing applications based on the polynomial abstraction technique. [Citation Graph (0, 0)][DBLP ] Conf ] Namrata Shekhar , Priyank Kalla , Florian Enescu , Sivaram Gopalakrishnan Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Ganapathy Parthasarathy , Madhu K. Iyer , Kwang-Ting Cheng , Forrest Brewer RTL SAT simplification by Boolean and interval arithmetic reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Mahmut T. Kandemir Runtime integrity checking for inter-object connections. [Citation Graph (0, 0)][DBLP ] Conf ] Huaizhi Wu , I-Min Liu , Martin D. F. Wong , Yusu Wang Post-placement voltage island generation under performance requirement. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Deng , Martin D. F. Wong Buffer insertion under process variations for delay minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiming Chen , Hai Zhou Efficient algorithms for buffer insertion in general circuits based on network flow. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan Lin , Hai Zhou Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Hyeonmin Lim , Kyungsoo Lee , Youngjin Cho , Naehyuck Chang Flip-flop insertion with shifted-phase clocks for FPGA power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Gupta , Charles Selvidge Acyclic modeling of combinational loops. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Zhong , Martin D. F. Wong Fast algorithms for IR drop analysis in large power grid. [Citation Graph (0, 0)][DBLP ] Conf ] Dionysios Kouroussis , Imad A. Ferzli , Farid N. Najm Incremental partitioning-based vectorless power grid verification. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Pant , David Blaauw Static timing analysis considering power supply variations. [Citation Graph (0, 0)][DBLP ] Conf ] André DeHon , Konstantin Likharev Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. [Citation Graph (0, 0)][DBLP ] Conf ] Navin Srivastava , Kaustav Banerjee Performance analysis of carbon nanotube interconnects for VLSI applications. [Citation Graph (0, 0)][DBLP ] Conf ] Di Wu , Ganesh Venkataraman , Jiang Hu , Quiyang Li , Rabi N. Mahapatra DiCER: distributed and cost-effective redundancy for variation tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Yasumasa Tsukamoto , Koji Nii , Susumu Imaoka , Yuji Oda , Shigeki Ohbayashi , Tomoaki Yoshizawa , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. [Citation Graph (0, 0)][DBLP ] Conf ] Suwen Yang , Mark R. Greenstreet Noise margin analysis for dynamic logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando De Bernardinis , Alberto L. Sangiovanni-Vincentelli Efficient analog platform characterization through analog constraint graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Jian Wang , Lawrence T. Pileggi , Tun-Shih Chen , Wanju Chiang Performance-centering optimization for system-level analog design exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Anuradha Agarwal , Ranga Vemuri Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Battery optimization vs energy optimization: which to choose and when? [Citation Graph (0, 0)][DBLP ] Conf ] Bren Mochocki , Razvan Racu , Rolf Ernst Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Seo , Taewhan Kim , Nikil D. Dutt Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. [Citation Graph (0, 0)][DBLP ] Conf ] Feihui Li , Guilin Chen , Mahmut T. Kandemir Compiler-directed voltage scaling on communication links for reducing power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Tamal Mukherjee Design automation issues for biofluidic microchips. [Citation Graph (0, 0)][DBLP ] Conf ] Paul W. K. Rothemund Design of DNA origami. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Dubrova , Maxim Teslenko , Andrés Martinelli Kauffman networks: analysis and applications. [Citation Graph (0, 0)][DBLP ] Conf ] Bradley Bond , Luca Daniel Parameterized model order reduction of nonlinear dynamical systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , C.-J. Richard Shi Fast-yet-accurate PVT simulation by combined direct and iterative methods. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Nieuwoudt , Yehia Massoud Robust automated synthesis methodology for integrated spiral inductors with variability. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Kumar Singh , Murari Mani , Michael Orshansky Statistical technology mapping for parametric yield. [Citation Graph (0, 0)][DBLP ] Conf ] Satrajit Chatterjee , Alan Mishchenko , Robert K. Brayton , Xinning Wang , Timothy Kam Reducing structural bias in technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Zhou , Bo Yao , Hongyu Chen , Yi Zhu , Chung-Kuan Cheng , Michael Hutton , Truman Collins , Sridhar Srinivasan , Nan-Chi Chou , Peter Suaris Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Suaris , Taeho Kgil , Keith A. Bowman , Vivek De , Trevor N. Mudge Total power-optimal pipelining and parallel processing under process variations in nanometer technology. [Citation Graph (0, 0)][DBLP ] Conf ] Maged Ghoneima , Yehea I. Ismail , Muhammad M. Khellah , James Tschanz , Vivek De Serial-link bus: a low-power on-chip bus architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stiff , Frank Vahid New decompilation techniques for binary-level co-processor generation. [Citation Graph (0, 0)][DBLP ] Conf ] Tamás Roska Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Amitabh Chaudhary , Danny Z. Chen , Kevin Whitton , Michael T. Niemier , Ramprasad Ravichandran Eliminating wire crossings for molecular quantum-dot cellular automata implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Liang Tsai , Lizheng Zhang Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Minsik Cho , Suhail Ahmed , David Z. Pan TACO: temperature aware clock-tree optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Ching Douglas Lam , J. Jam , Cheng-Kok Koh , Venkataramanan Balakrishnan , Yiran Chen Statistical based link insertion for robust clock network design. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Venkataraman , Nikhil Jayakumar , Jiang Hu , Peng Li , Sunil P. Khatri , Anand Rajaram , Patrick McGuinness , Charles J. Alpert Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ting Mei , Jaijeet S. Roychowdhury An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Ting Mei , Jaijeet S. Roychowdhury Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Kapil D. Boianapally , Ting Mei , Jaijeet S. Roychowdhury A multi-harmonic probe technique for computing oscillator steady states. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Mehrotra , Suihua Lu , David C. Lee , Amit Narayan Steady-state analysis of voltage and current controlled oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Yang Yeh , Malgorzata Marek-Sadowska Timing-aware power noise reduction in layout. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Zhan , Sachin S. Sapatnekar A high efficiency full-chip thermal simulation algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Pu Liu , Zhenyu Qi , Hang Li , Lingling Jin , Wei Wu , Sheldon X.-D. Tan , Jun Yang Fast thermal simulation for architecture level dynamic thermal management. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality. [Citation Graph (0, 0)][DBLP ] Conf ] Seth Copen Goldstein The impact of the nanoscale on computing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Dwyer Computer-aided design for DNA self-assembly: process and applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori A mapping algorithm for defect-tolerance of reconfigurable nano-architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenhai Zhu , Jacob K. White FastSies: a fast stochastic integral equation solver for modeling the rough surface effect. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Jiang , Wenyin Fu , Janet Meiling Wang , Vince Lin , Charlie Chung-Ping Chen Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mosin Mondal , Yehia Massoud Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance. [Citation Graph (0, 0)][DBLP ] Conf ] Yaping Zhan , Andrzej J. Strojwas , Mahesh Sharma , David Newmark Statistical critical path analysis considering correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Saumil Shah , Ashish Srivastava , Dushyant Sharma , Dennis Sylvester , David Blaauw , Vladimir Zolotov Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Jiayong Le , Lawrence T. Pileggi , Andrzej J. Strojwas Projection-based performance modeling for inter/intra-die variations. [Citation Graph (0, 0)][DBLP ] Conf ] Janet Meiling Wang , Bharat Srinivas , Dongsheng Ma , Charlie Chung-Ping Chen , Jun Li System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). [Citation Graph (0, 0)][DBLP ] Conf ] Amit Agarwal , Kunhyuk Kang , Kaushik Roy Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yan Zhang Thermal via planning for 3-D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jia-Wei Fang , I-Jye Lin , Ping-Hung Yuh , Yao-Wen Chang , Jyh-Herng Wang A routing algorithm for flip-chip design. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong , Philip S. Honsinger An escape routing framework for dense boards with high-speed design constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong , Philip S. Honsinger Optimal routing algorithms for pin clusters in high-density multichip modules. [Citation Graph (0, 0)][DBLP ] Conf ] Aravind Vijayakumar , Forrest Brewer Weighted control scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel L. Rosenband Hardware synthesis from guarded atomic actions with performance specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Love Singhal , Elaheh Bozorgzadeh Fast timing closure by interconnect criticality driven delay relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Ngai Wong , Venkataramanan Balakrishnan Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Peng Li , Lawrence T. Pileggi Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Vasilyev , Jacob K. White A more reliable reduction algorithm for behavioral model extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Pu Liu , Sheldon X.-D. Tan , Hang Li , Zhenyu Qi , Jun Kong , Bruce McGaughy , Lei He An efficient method for terminal reduction of interconnect circuits considering delay variations. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled R. Heloue , Farid N. Najm Statistical timing analysis with two-sided constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , Hai Zhou A unified framework for statistical timing analysis with coupling and multiple input switching. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Jiayong Le , Mustafa Celik , Lawrence T. Pileggi Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. [Citation Graph (0, 0)][DBLP ] Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan Verification of executable pipelined machines with bit-level interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan A complete compositional reasoning framework for the efficient verification of pipelined machines. [Citation Graph (0, 0)][DBLP ] Conf ] Moayad Fahim Ali , Sean Safarpour , Andreas G. Veneris , Magdy S. Abadir , Rolf Drechsler Post-verification debugging of hierarchical designs. [Citation Graph (0, 0)][DBLP ] Conf ] Roy Armoni , Sergey Egorov , Ranan Fraer , Dmitry Korchemny , Moshe Y. Vardi Efficient LTL compilation for SAT-based model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Suchismita Roy , Sayantan Das , Prasenjit Basu , Pallab Dasgupta , Partha Pratim Chakrabarti SAT based solutions for consistency problems in formal property specifications for open systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sherief Reda , Qinke Wang Architecture and details of a high quality, large-scale analytical placer. [Citation Graph (0, 0)][DBLP ] Conf ] Kristofer Vorwerk , Andrew A. Kennings Mixed-size placement via line search. [Citation Graph (0, 0)][DBLP ] Conf ] Haifeng Qian , Sachin S. Sapatnekar A hybrid linear equation solver and its application in quadratic placement. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Chulsung Park Energy-efficient platform designs for real-world wireless sensing applications. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Schott , Michael Bajura Power-aware microsensor design. [Citation Graph (0, 0)][DBLP ] Conf ] Prabal Dutta , David E. Culler System software techniques for low-power operation in wireless sensor networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed M. Shebaita , Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail Expanding the frequency range of AWE via time shifting. [Citation Graph (0, 0)][DBLP ] Conf ] Hongyu Chen , Chao-Yang Yeh , Gustavo R. Wilke , Subodh M. Reddy , Hoa-van Nguyen , William W. Walker , Rajeev Murgai A sliding window scheme for accurate clock mesh analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Jain , David Blaauw , Vladimir Zolotov Accurate delay computation for noisy waveform shapes. [Citation Graph (0, 0)][DBLP ] Conf ] Murat R. Becer , Vladimir Zolotov , Rajendran Panda , Amir Grinshpon , Ilan Algor , Rafi Levy , Chanhee Oh Pessimism reduction in crosstalk noise aware STA. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred Koelbl , Yuan Lu , Anmol Mathur Embedded tutorial: formal equivalence checking between system-level models and RTL. [Citation Graph (0, 0)][DBLP ] Conf ] M. Frank Chang CDMA/FDMA-interconnects for future ULSI communications. [Citation Graph (0, 0)][DBLP ] Conf ] K. O. Kenneth , Kihong Kim , Brian A. Floyd , Jesal L. Mehta , Hyun Yoon , Chih-Ming Hung , Daniel F. Bravo , Timothy O. Dickson , Xiaoling Guo , Ran Li , Narasimhan Trichy , James Caserta , Wayne R. Bomstad II , Jason Branch , Dong-Jun Yang , Jose Bohorquez , Jie Chen , Eunyoung Seok , Li Gao , Aravind Sugavanam , Jau-Jr Lin , S. Yu , C. Cao , M.-H. Hwang , Y.-R. Ding , S.-H. Hwang , H. Wu , N. Zhang , Joe E. Brewer The feasibility of on-chip interconnection using antennas. [Citation Graph (0, 0)][DBLP ] Conf ] Michael P. Flynn , Joshua Jaeyoung Kang Global signaling over lossy transmission lines. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Ishihara , Farzan Fallah A cache-defect-aware code placement algorithm for improving the performance of processors. [Citation Graph (0, 0)][DBLP ] Conf ] Feihui Li , Guilin Chen , Mahmut T. Kandemir , Ibrahim Kolcu Improving scratch-pad memory reliability through compiler-guided data block duplication. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Agiwal , Montek Singh An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems. [Citation Graph (0, 0)][DBLP ] Conf ] Montek Singh Memory access optimization of dynamic binary translation for reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kaviraj Chopra , Saumil Shah , Ashish Srivastava , David Blaauw , Dennis Sylvester Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew R. Guthaus , Natesan Venkateswaran , Chandu Visweswariah , Vladimir Zolotov Gate sizing using incremental parameterized statistical timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , Narendra V. Shenoy , Hai Zhou Statistical gate sizing for timing yield optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Hui Chang , Valeria Bertacco , Igor L. Markov Simulation-based bug trace minimization with BMC-based refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Alphan Bayazit , Sharad Malik Complementary use of runtime validation and model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Zaraket , Jason Baumgartner , Adnan Aziz Scalable compositional minimization via static analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Minh D. Nguyen , Dominik Stoffel , Markus Wedler , Wolfgang Kunz Transition-by-transition FSM traversal for reachability analysis in bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Per Bjesse , James H. Kukula Automatic generalized phase abstraction for formal verification. [Citation Graph (0, 0)][DBLP ] Conf ] 