Conferences in DBLP
Wenrui Gong , Gang Wang , Ryan Kastner Storage assignment during high-level synthesis for configurable architectures. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:3-6 [Conf ] Rafael Ruiz-Sautua , María C. Molina , Jose Manuel Mendias , Román Hermida Performance-driven read-after-write dependencies softening in high-level synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:7-12 [Conf ] Paulo F. Flores , José C. Monteiro , Eduardo A. C. da Costa An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:13-16 [Conf ] Ho-Yan Wong , Lerong Cheng , Yan Lin , Lei He FPGA device and architecture evaluation considering process variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:19-24 [Conf ] Yajun Ran , Malgorzata Marek-Sadowska Via-configurable routing architectures and fast design mappability estimation for regular fabrics. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:25-32 [Conf ] Kwok-Shing Leung SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:33-38 [Conf ] Tao Luo , Haoxing Ren , Charles J. Alpert , David Zhigang Pan Computational geometry based placement migration. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:41-47 [Conf ] Min Pan , Natarajan Viswanathan , Chris C. N. Chu An efficient and effective detailed placement algorithm. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:48-55 [Conf ] Kai-Hui Chang , Igor L. Markov , Valeria Bertacco Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:56-63 [Conf ] Xin Hao , Forrest Brewer Wirelength optimization by optimal block orientation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:64-70 [Conf ] Erkan Acar , Sule Ozev Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:73-79 [Conf ] Mango Chia-Tso Chao , Seongmoon Wang , Srimat T. Chakradhar , Kwang-Ting Cheng Response shaper: a novel technique to enhance unknown tolerance for output response compaction. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:80-87 [Conf ] Anuja Sehgal , Krishnendu Chakrabarty Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:88-93 [Conf ] Krishnendu Chakrabarty , J. E. Chen A cocktail approach on random access scan toward low power and high efficiency test. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:94-99 [Conf ] David Bordoley , Hieu Nguyen , Mani Soma A statistical study of the effectiveness of BIST jitter measurement techniques. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:100-107 [Conf ] Osamu Takahashi , Russ Cook , Scott R. Cottier , Sang H. Dhong , Brian K. Flachs , Koji Hirairi , Atsushi Kawasumi , Hiroaki Murakami , Hiromi Noro , Hwa-Joon Oh , S. Onish , Juergen Pille , Joel Silberman The circuit design of the synergistic processor element of a CELL processor. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:111-117 [Conf ] Richard McGowen Adaptive designs for power and thermal optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:118-121 [Conf ] Robert B. Staszewski , Khurram Muhammad , Dirk Leipold Digital RF processor (DRP/spl trade/) for cellular phones. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:122-129 [Conf ] Jianfeng Luo , Qing Su , Charles Chiang , Jamil Kawa A layout dependent full-chip copper electroplating topography model. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:133-140 [Conf ] James D. Ma , Claire Fang Fang , Rob A. Rutenbar , Xiaolin Xie , Duane S. Boning Interval-valued statistical modeling of oxide chemical-mechanical polishing. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:141-148 [Conf ] Charles Chiang , Andrew B. Kahng , Subarna Sinha , Xu Xu Fast and efficient phase conflict detection and correction in standard-cell layouts. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:149-156 [Conf ] Tung-Chieh Chen , Yao-Wen Chang , Shyh-Chang Lin IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:159-164 [Conf ] Jason Cong , Michail Romesis , Joseph R. Shinnerl Robust mixed-size placement under tight white-space constraints. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:165-172 [Conf ] Andrew B. Kahng , Sherief Reda Intrinsic shortest path length: a new, accurate a priori wirelength estimator. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:173-180 [Conf ] Yinghua Li , Alex Kondratyev , Robert K. Brayton Synthesis methodology for built-in at-speed testing. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:183-188 [Conf ] Chuan Lin , Jia Wang , Hai Zhou Clustering for processing rate optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:189-195 [Conf ] Sanghamitra Roy , Weijen Chen ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:196-203 [Conf ] Tsu-Jae King FinFETs for nanoscale CMOS digital integrated circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:207-210 [Conf ] Vishal P. Trivedi , Jerry G. Fossum , Leo Mathew , Murshed M. Chowdhury , Weimin Zhang , Glenn O. Workman , Bich-Yen Nguyen Physics-based compact modeling for nonclassical CMOS. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:211-216 [Conf ] Kaushik Roy , Hamid Mahmoodi-Meimand , Saibal Mukhopadhyay , Hari Ananthan , Aditya Bansal , Tamer Cakici Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:217-224 [Conf ] Jeremy A. Rowlette , Eric Pop , Sanjiv Sinha , Mathew Panzer , Kenneth E. Goodson Thermal simulation techniques for nanoscale transistors. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:225-228 [Conf ] Krishnan Srinivasan , Karam S. Chatha , Goran Konjevod An automated technique for topology and route generation of application specific on-chip interconnection networks. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:231-237 [Conf ] Martin K. F. Schafer , Thomas Hollstein , Heiko Zimmer , Manfred Glesner Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:238-245 [Conf ] Ümit Y. Ogras , Radu Marculescu Application-specific network-on-chip architecture customization via long-range link insertion. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:246-253 [Conf ] Jeremy Chan , Sri Parameswaran NoCEE: energy macro-model extraction methodology for network on chip routers. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:254-259 [Conf ] Jason Cong , Guoling Han , Zhiru Zhang Architecture and compilation for data bandwidth improvement in configurable embedded processors. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:263-270 [Conf ] Guilin Chen , Mahmut T. Kandemir Code restructuring for improving cache performance of MPSoCs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:271-274 [Conf ] Mahmut T. Kandemir 2D data locality: definition, abstraction, and application. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:275-278 [Conf ] Guilin Chen , Ozcan Ozturk , Mahmut T. Kandemir , Ibrahim Kolcu Integrating loop and data optimizations for locality within a constraint network based framework. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:279-282 [Conf ] Tarvo Raudvere , Ashish Kumar Singh , Ingo Sander , Axel Jantsch System level verification of digital signal processing applications based on the polynomial abstraction technique. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:285-290 [Conf ] Namrata Shekhar , Priyank Kalla , Florian Enescu , Sivaram Gopalakrishnan Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:291-296 [Conf ] Ganapathy Parthasarathy , Madhu K. Iyer , Kwang-Ting Cheng , Forrest Brewer RTL SAT simplification by Boolean and interval arithmetic reasoning. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:297-302 [Conf ] Guilin Chen , Mahmut T. Kandemir Runtime integrity checking for inter-object connections. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:303-306 [Conf ] Huaizhi Wu , I-Min Liu , Martin D. F. Wong , Yusu Wang Post-placement voltage island generation under performance requirement. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:309-316 [Conf ] Liang Deng , Martin D. F. Wong Buffer insertion under process variations for delay minimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:317-321 [Conf ] Ruiming Chen , Hai Zhou Efficient algorithms for buffer insertion in general circuits based on network flow. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:322-326 [Conf ] Chuan Lin , Hai Zhou Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:329-334 [Conf ] Hyeonmin Lim , Kyungsoo Lee , Youngjin Cho , Naehyuck Chang Flip-flop insertion with shifted-phase clocks for FPGA power reduction. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:335-342 [Conf ] Amit Gupta , Charles Selvidge Acyclic modeling of combinational loops. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:343-347 [Conf ] Yu Zhong , Martin D. F. Wong Fast algorithms for IR drop analysis in large power grid. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:351-357 [Conf ] Dionysios Kouroussis , Imad A. Ferzli , Farid N. Najm Incremental partitioning-based vectorless power grid verification. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:358-364 [Conf ] Sanjay Pant , David Blaauw Static timing analysis considering power supply variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:365-371 [Conf ] André DeHon , Konstantin Likharev Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:375-382 [Conf ] Navin Srivastava , Kaustav Banerjee Performance analysis of carbon nanotube interconnects for VLSI applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:383-390 [Conf ] Di Wu , Ganesh Venkataraman , Jiang Hu , Quiyang Li , Rabi N. Mahapatra DiCER: distributed and cost-effective redundancy for variation tolerance. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:393-397 [Conf ] Yasumasa Tsukamoto , Koji Nii , Susumu Imaoka , Yuji Oda , Shigeki Ohbayashi , Tomoaki Yoshizawa , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:398-405 [Conf ] Suwen Yang , Mark R. Greenstreet Noise margin analysis for dynamic logic circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:406-412 [Conf ] Fernando De Bernardinis , Alberto L. Sangiovanni-Vincentelli Efficient analog platform characterization through analog constraint graphs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:415-421 [Conf ] Xin Li , Jian Wang , Lawrence T. Pileggi , Tun-Shih Chen , Wanju Chiang Performance-centering optimization for system-level analog design exploration. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:422-429 [Conf ] Anuradha Agarwal , Ranga Vemuri Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:430-436 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Battery optimization vs energy optimization: which to choose and when? [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:439-445 [Conf ] Bren Mochocki , Razvan Racu , Rolf Ernst Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:446-449 [Conf ] Jaewon Seo , Taewhan Kim , Nikil D. Dutt Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:450-455 [Conf ] Feihui Li , Guilin Chen , Mahmut T. Kandemir Compiler-directed voltage scaling on communication links for reducing power consumption. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:456-460 [Conf ] Tamal Mukherjee Design automation issues for biofluidic microchips. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:463-470 [Conf ] Paul W. K. Rothemund Design of DNA origami. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:471-478 [Conf ] Elena Dubrova , Maxim Teslenko , Andrés Martinelli Kauffman networks: analysis and applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:479-484 [Conf ] Bradley Bond , Luca Daniel Parameterized model order reduction of nonlinear dynamical systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:487-494 [Conf ] Bo Hu , C.-J. Richard Shi Fast-yet-accurate PVT simulation by combined direct and iterative methods. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:495-501 [Conf ] Arthur Nieuwoudt , Yehia Massoud Robust automated synthesis methodology for integrated spiral inductors with variability. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:502-507 [Conf ] Ashish Kumar Singh , Murari Mani , Michael Orshansky Statistical technology mapping for parametric yield. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:511-518 [Conf ] Satrajit Chatterjee , Alan Mishchenko , Robert K. Brayton , Xinning Wang , Timothy Kam Reducing structural bias in technology mapping. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:519-526 [Conf ] Shuo Zhou , Bo Yao , Hongyu Chen , Yi Zhu , Chung-Kuan Cheng , Michael Hutton , Truman Collins , Sridhar Srinivasan , Nan-Chi Chou , Peter Suaris Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:527-531 [Conf ] Peter Suaris , Taeho Kgil , Keith A. Bowman , Vivek De , Trevor N. Mudge Total power-optimal pipelining and parallel processing under process variations in nanometer technology. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:535-540 [Conf ] Maged Ghoneima , Yehea I. Ismail , Muhammad M. Khellah , James Tschanz , Vivek De Serial-link bus: a low-power on-chip bus architecture. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:541-546 [Conf ] Greg Stiff , Frank Vahid New decompilation techniques for binary-level co-processor generation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:547-554 [Conf ] Tamás Roska Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:557-564 [Conf ] Amitabh Chaudhary , Danny Z. Chen , Kevin Whitton , Michael T. Niemier , Ramprasad Ravichandran Eliminating wire crossings for molecular quantum-dot cellular automata implementation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:565-571 [Conf ] Jeng-Liang Tsai , Lizheng Zhang Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:575-581 [Conf ] Minsik Cho , Suhail Ahmed , David Z. Pan TACO: temperature aware clock-tree optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:582-587 [Conf ] Wai-Ching Douglas Lam , J. Jam , Cheng-Kok Koh , Venkataramanan Balakrishnan , Yiran Chen Statistical based link insertion for robust clock network design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:588-591 [Conf ] Ganesh Venkataraman , Nikhil Jayakumar , Jiang Hu , Peng Li , Sunil P. Khatri , Anand Rajaram , Patrick McGuinness , Charles J. Alpert Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:592-596 [Conf ] Ting Mei , Jaijeet S. Roychowdhury An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:599-603 [Conf ] Ting Mei , Jaijeet S. Roychowdhury Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:604-609 [Conf ] Kapil D. Boianapally , Ting Mei , Jaijeet S. Roychowdhury A multi-harmonic probe technique for computing oscillator steady states. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:610-613 [Conf ] Amit Mehrotra , Suihua Lu , David C. Lee , Amit Narayan Steady-state analysis of voltage and current controlled oscillators. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:618-623 [Conf ] Chao-Yang Yeh , Malgorzata Marek-Sadowska Timing-aware power noise reduction in layout. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:627-634 [Conf ] Yong Zhan , Sachin S. Sapatnekar A high efficiency full-chip thermal simulation algorithm. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:635-638 [Conf ] Pu Liu , Zhenyu Qi , Hang Li , Lingling Jin , Wei Wu , Sheldon X.-D. Tan , Jun Yang Fast thermal simulation for architecture level dynamic thermal management. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:639-644 [Conf ] Peng Li Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:645-651 [Conf ] Seth Copen Goldstein The impact of the nanoscale on computing systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:655-661 [Conf ] Chris Dwyer Computer-aided design for DNA self-assembly: process and applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:662-667 [Conf ] Mehdi Baradaran Tahoori A mapping algorithm for defect-tolerance of reconfigurable nano-architectures. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:668-672 [Conf ] Zhenhai Zhu , Jacob K. White FastSies: a fast stochastic integral equation solver for modeling the rough surface effect. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:675-682 [Conf ] Rong Jiang , Wenyin Fu , Janet Meiling Wang , Vince Lin , Charlie Chung-Ping Chen Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:683-690 [Conf ] Mosin Mondal , Yehia Massoud Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:691-696 [Conf ] Yaping Zhan , Andrzej J. Strojwas , Mahesh Sharma , David Newmark Statistical critical path analysis considering correlations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:699-704 [Conf ] Saumil Shah , Ashish Srivastava , Dushyant Sharma , Dennis Sylvester , David Blaauw , Vladimir Zolotov Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:705-712 [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:713-718 [Conf ] Xin Li , Jiayong Le , Lawrence T. Pileggi , Andrzej J. Strojwas Projection-based performance modeling for inter/intra-die variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:721-727 [Conf ] Janet Meiling Wang , Bharat Srinivas , Dongsheng Ma , Charlie Chung-Ping Chen , Jun Li System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:728-735 [Conf ] Amit Agarwal , Kunhyuk Kang , Kaushik Roy Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:736-741 [Conf ] Jason Cong , Yan Zhang Thermal via planning for 3-D ICs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:745-752 [Conf ] Jia-Wei Fang , I-Jye Lin , Ping-Hung Yuh , Yao-Wen Chang , Jyh-Herng Wang A routing algorithm for flip-chip design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:753-758 [Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong , Philip S. Honsinger An escape routing framework for dense boards with high-speed design constraints. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:759-766 [Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong , Philip S. Honsinger Optimal routing algorithms for pin clusters in high-density multichip modules. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:767-774 [Conf ] Aravind Vijayakumar , Forrest Brewer Weighted control scheduling. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:777-783 [Conf ] Daniel L. Rosenband Hardware synthesis from guarded atomic actions with performance specifications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:784-791 [Conf ] Love Singhal , Elaheh Bozorgzadeh Fast timing closure by interconnect criticality driven delay relaxation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:792-797 [Conf ] Ngai Wong , Venkataramanan Balakrishnan Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:801-805 [Conf ] Xin Li , Peng Li , Lawrence T. Pileggi Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:806-812 [Conf ] Dmitry Vasilyev , Jacob K. White A more reliable reduction algorithm for behavioral model extraction. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:813-820 [Conf ] Pu Liu , Sheldon X.-D. Tan , Hang Li , Zhenyu Qi , Jun Kong , Bruce McGaughy , Lei He An efficient method for terminal reduction of interconnect circuits considering delay variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:821-826 [Conf ] Khaled R. Heloue , Farid N. Najm Statistical timing analysis with two-sided constraints. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:829-836 [Conf ] Debjit Sinha , Hai Zhou A unified framework for statistical timing analysis with coupling and multiple input switching. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:837-843 [Conf ] Xin Li , Jiayong Le , Mustafa Celik , Lawrence T. Pileggi Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:844-851 [Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan Verification of executable pipelined machines with bit-level interfaces. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:855-862 [Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan A complete compositional reasoning framework for the efficient verification of pipelined machines. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:863-870 [Conf ] Moayad Fahim Ali , Sean Safarpour , Andreas G. Veneris , Magdy S. Abadir , Rolf Drechsler Post-verification debugging of hierarchical designs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:871-876 [Conf ] Roy Armoni , Sergey Egorov , Ranan Fraer , Dmitry Korchemny , Moshe Y. Vardi Efficient LTL compilation for SAT-based model checking. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:877-884 [Conf ] Suchismita Roy , Sayantan Das , Prasenjit Basu , Pallab Dasgupta , Partha Pratim Chakrabarti SAT based solutions for consistency problems in formal property specifications for open systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:885-888 [Conf ] Andrew B. Kahng , Sherief Reda , Qinke Wang Architecture and details of a high quality, large-scale analytical placer. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:891-898 [Conf ] Kristofer Vorwerk , Andrew A. Kennings Mixed-size placement via line search. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:899-904 [Conf ] Haifeng Qian , Sachin S. Sapatnekar A hybrid linear equation solver and its application in quadratic placement. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:905-909 [Conf ] Pai H. Chou , Chulsung Park Energy-efficient platform designs for real-world wireless sensing applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:913-920 [Conf ] Brian Schott , Michael Bajura Power-aware microsensor design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:921-924 [Conf ] Prabal Dutta , David E. Culler System software techniques for low-power operation in wireless sensor networks. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:925-932 [Conf ] Ahmed M. Shebaita , Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail Expanding the frequency range of AWE via time shifting. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:935-938 [Conf ] Hongyu Chen , Chao-Yang Yeh , Gustavo R. Wilke , Subodh M. Reddy , Hoa-van Nguyen , William W. Walker , Rajeev Murgai A sliding window scheme for accurate clock mesh analysis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:939-946 [Conf ] Amit Jain , David Blaauw , Vladimir Zolotov Accurate delay computation for noisy waveform shapes. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:947-953 [Conf ] Murat R. Becer , Vladimir Zolotov , Rajendran Panda , Amir Grinshpon , Ilan Algor , Rafi Levy , Chanhee Oh Pessimism reduction in crosstalk noise aware STA. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:954-961 [Conf ] Alfred Koelbl , Yuan Lu , Anmol Mathur Embedded tutorial: formal equivalence checking between system-level models and RTL. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:965-971 [Conf ] M. Frank Chang CDMA/FDMA-interconnects for future ULSI communications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:975-978 [Conf ] K. O. Kenneth , Kihong Kim , Brian A. Floyd , Jesal L. Mehta , Hyun Yoon , Chih-Ming Hung , Daniel F. Bravo , Timothy O. Dickson , Xiaoling Guo , Ran Li , Narasimhan Trichy , James Caserta , Wayne R. Bomstad II , Jason Branch , Dong-Jun Yang , Jose Bohorquez , Jie Chen , Eunyoung Seok , Li Gao , Aravind Sugavanam , Jau-Jr Lin , S. Yu , C. Cao , M.-H. Hwang , Y.-R. Ding , S.-H. Hwang , H. Wu , N. Zhang , Joe E. Brewer The feasibility of on-chip interconnection using antennas. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:979-984 [Conf ] Michael P. Flynn , Joshua Jaeyoung Kang Global signaling over lossy transmission lines. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:985-992 [Conf ] Tohru Ishihara , Farzan Fallah A cache-defect-aware code placement algorithm for improving the performance of processors. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:995-1001 [Conf ] Feihui Li , Guilin Chen , Mahmut T. Kandemir , Ibrahim Kolcu Improving scratch-pad memory reliability through compiler-guided data block duplication. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1002-1005 [Conf ] Ankur Agiwal , Montek Singh An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1006-1013 [Conf ] Montek Singh Memory access optimization of dynamic binary translation for reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1014-1020 [Conf ] Kaviraj Chopra , Saumil Shah , Ashish Srivastava , David Blaauw , Dennis Sylvester Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1023-1028 [Conf ] Matthew R. Guthaus , Natesan Venkateswaran , Chandu Visweswariah , Vladimir Zolotov Gate sizing using incremental parameterized statistical timing analysis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1029-1036 [Conf ] Debjit Sinha , Narendra V. Shenoy , Hai Zhou Statistical gate sizing for timing yield optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1037-1041 [Conf ] Kai-Hui Chang , Valeria Bertacco , Igor L. Markov Simulation-based bug trace minimization with BMC-based refinement. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1045-1051 [Conf ] Ali Alphan Bayazit , Sharad Malik Complementary use of runtime validation and model checking. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1052-1059 [Conf ] Fadi A. Zaraket , Jason Baumgartner , Adnan Aziz Scalable compositional minimization via static analysis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1060-1067 [Conf ] Minh D. Nguyen , Dominik Stoffel , Markus Wedler , Wolfgang Kunz Transition-by-transition FSM traversal for reachability analysis in bounded model checking. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1068-1075 [Conf ] Per Bjesse , James H. Kukula Automatic generalized phase abstraction for formal verification. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1076-1082 [Conf ]