Conferences in DBLP
Jason Cong , Sung Kyu Lim Physical Planning with Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung-Kuan Cheng , Jun Gu Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. [Citation Graph (0, 0)][DBLP ] Conf ] Florin Balasa Modeling Non-Slicing Floorplans with Binary Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Stefanus Mantik On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer Event Driven Simulation Without Loops or Conditionals. [Citation Graph (0, 0)][DBLP ] Conf ] José C. Costa , Srinivas Devadas , José Monteiro Observability Analysis of Embedded Software for Coverage-Directed Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Gernot Koch , Taewhan Kim , Reiner Genevriere A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Farinaz Koushanfar , Darko Kirovski , Miodrag Potkonjak Symbolic Debugging Scheme for Optimized Hardware and Software. [Citation Graph (0, 0)][DBLP ] Conf ] Per Gunnar Kjeldsberg , Francky Catthoor , Einar J. Aas Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. [Citation Graph (0, 0)][DBLP ] Conf ] Hyeong-Ju Kang , Hansoo Kim , In-Cheol Park FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Sudhakar Muddu , Dirk Stroobandt , Dennis Sylvester Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Orshansky , Linda Milor , Pinhong Chen , Kurt Keutzer , Chenming Hu Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Pinhong Chen , Desmond Kirkpatrick , Kurt Keutzer Miller Factor for Gate-Level Coupling Delay Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey , Miodrag Potkonjak , Farinaz Koushanfar , Suet-Fei Li , Tim Tuan Challenges and Opportunities in Broadband and Wireless Communication Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph H. J. M. Otten , Paul Stravers Challenges in Physical Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbing Fan , Jiping Liu , Yu-Liang Wu General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jiang Hu , Sachin S. Sapatnekar A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Feodor F. Dragan , Andrew B. Kahng , Ion I. Mandoiu , Sudhakar Muddu , Alexander Zelikovsky Provably Good Global Buffering Using an Available Buffer Block Plan. [Citation Graph (0, 0)][DBLP ] Conf ] Ryan Kastner , Elaheh Bozorgzadeh , Majid Sarrafzadeh Predictable Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar G. Govindaraju , David L. Dill Counterexample-Guided Choice of Projections in Approximate Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Hsin Ho , Thomas R. Shiple , Kevin Harer , James H. Kukula , Robert F. Damiano , Valeria Bertacco , Jerry Taylor , Jiang Long Smart Simulation Using Collaborative Formal and Simulation Engines. [Citation Graph (0, 0)][DBLP ] Conf ] C. Norris Ip Simulation Coverage Enhancement Using Test Stimulus Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Ziegenbein , Jan Uerpmann , Ralph Ernst Dynamic Response Time Optimization for SDF Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard , Dipak Sitaram , Yu Zheng Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Hao Ji , Wayne Wei-Ming Dai How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. [Citation Graph (0, 0)][DBLP ] Conf ] Charlie Chung-Ping Chen , Tae-Woo Lee , Narayanan Murugesan , Susan C. Hagness Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Woo Hur , John Lillis MONGREL: Hybrid Techniques for Standard Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Chan , Jason Cong , Tianming Kong , Joseph R. Shinnerl Multilevel Optimization for Large-Scale Circuit Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Abdallah Tabbara , Robert K. Brayton A Force-Directed Macro-Cell Placer. [Citation Graph (0, 0)][DBLP ] Conf ] Jeongjin Roh , Suresh Seshadri , Jacob A. Abraham Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Francken , Peter J. Vancorenland , Georges G. E. Gielen DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Lauwers , Georges G. E. Gielen ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhong Chen , Xiaojian Yang , Majid Sarrafzadeh Potential Slack: An Effective Metric of Combinational Circuit Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Chu Kuo , Allen C.-H. Wu Delay Budgeting for a Timing-Closure-Driven Design Method. [Citation Graph (0, 0)][DBLP ] Conf ] Rongtian Zhang , Kaushik Roy , Cheng-Kok Koh , David B. Janes Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael W. Beattie , Satrajit Gupta , Lawrence T. Pileggi Hierarchical Interconnect Circuit Models. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Yang , Chung-Kuan Cheng , Walter H. Ku , Robert J. Carragher Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli V. Kashyap , Charles J. Alpert , Anirudh Devgan An "Effective" Capacitance Based Delay Metric for RC Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Jason Cong , Sharad Malik , Majid Sarrafzadeh Incremental CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas A. Henzinger , Shaz Qadeer , Sriram K. Rajamani Decomposing Refinement Proofs Using Assume-Guarantee Reasoning. [Citation Graph (0, 0)][DBLP ] Conf ] Ke Zhong , Shantanu Dutt Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. [Citation Graph (0, 0)][DBLP ] Conf ] Maogang Wang , Xiaojian Yang , Majid Sarrafzadeh DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Terry Tao Ye , Giovanni De Micheli Data Path Placement with Regularity. [Citation Graph (0, 0)][DBLP ] Conf ] Baolin Yang , Dan Feng Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal Analyses. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Mehrotra Noise Analysis of Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Demir , David E. Long , Jaijeet S. Roychowdhury Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Demir , Peter Feldmann Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Sangyun Kim , Peter A. Beerel Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Hans M. Jacobson , Chris J. Myers , Ganesh Gopalakrishnan Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Sungpack Hong , Taewhan Kim Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Wook Kim , Kwang-Hyun Baek , Naresh R. Shanbhag , C. L. (Dave) Liu , Sung-Mo Kang Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. [Citation Graph (0, 0)][DBLP ] Conf ] Paul-Peter Sotiriadis , Anantha Chandrakasan Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Bechtolsheim , Joe Costello , Aart de Gues , Patrick Scaglia , Jennifer Smith Why Doesn't EDA Get Enough Respect? [Citation Graph (0, 0)][DBLP ] Conf ] Pinhong Chen , Desmond Kirkpatrick , Kurt Keutzer Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Chanhee Oh , Rajendran Panda Slope Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Pawan Kulshreshtha , Robert Palermo , Mohammad Mortazavi , Cyrus Bamji , Hakan Yalcin Transistor-Level Timing Analysis Using Embedded Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Ramanathan , Sandy Irani , Rajesh K. Gupta Latency Effects of System Level Power Management Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jiong Luo , Niraj K. Jha Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Kiyoung Choi , Takayasu Sakurai Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Qiushuang Zhang , Ian G. Harris A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Chen , Cheng-Ta Hsieh , Massoud Pedram Simultaneous Gate Sizing and Fanout Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai Layout-Driven Area-Constrained Timing Optimization by Net Buffering. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Hwa Cheng , Shih-Chieh Chang , Shin-De Li , Wen-Ben Jone , Jinn-Shyan Wang Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian , Sujit Dey , Mike Rodgers Test of Future System-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Wen Albert Tsao , Cheng-Kok Koh UST/DME: A Clock Tree Router for General Skew Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Guoan Zhong , Cheng-Kok Koh , Kaushik Roy A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil P. Khatri , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. [Citation Graph (0, 0)][DBLP ] Conf ] Milenko Drinic , Darko Kirovski , Seapahn Meguerdichian , Miodrag Potkonjak Latency-Guided On-Chip Bus Network Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kanishka Lahiri , Anand Raghunathan , Sujit Dey Efficient Exploration of the SoC Communication Architecture Design Space. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau MIST: An Algorithm for Memory Miss Traffic Management. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Kutzschebauch , Leon Stok Regularity Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Srivastava , Ryan Kastner , Majid Sarrafzadeh Timing Driven Gate Duplication: Complexity Issues and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Arlindo L. Oliveira , Rajeev Murgai An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Irith Pomeranz , Sudhakar M. Reddy , Janusz Rajski Improving the Proportion of At-Speed Tests in Scan BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Seonki Kim , Bapiraju Vinnakota Fast Test Application Technique Without Fast Scan Clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Feng Wu , Chih-Tsun Huang , Chih-Wea Wang , Kuo-Liang Cheng , Cheng-Wen Wu Error Catch and Analysis for Semiconductor Memories Using March Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Ian G. Harris , Russell Tessier Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Su , Kaushik Gala , Sachin S. Sapatnekar Fast Analysis and Optimization of Power/Ground Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj Simulation and Optimization of the Power Distribution Network in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyou Zhao , Kaushik Roy , Cheng-Kok Koh Frequency Domain Analysis of Switching Noise on Power Supply Network. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jia Liou , Angela Krstic , Yi-Min Jiang , Kwang-Ting Cheng Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Mariagiovanna Sami , Donatella Sciuto , Cristina Silvano , Vittorio Zaccaria Power Exploration for Embedded VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Margarida F. Jacome , Gustavo de Veciana , Viktor S. Lapinskii Exploring Performance Tradeoffs for Clustered VLIW ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] James C. Hoe , Arvind Synthesis of Operation-Centric Hardware Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Yunjian Jiang , Robert K. Brayton Don't Cares and Multi-Valued Logic Network Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Victor N. Kravets , Karem A. Sakallah Generalized Symmetries in Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , Zhong-Zhen Wu , He-Zhe Yu Wire Reconnections Based on Implication Flow Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Ilker Hamzaoglu , Janak H. Patel Deterministic Test Pattern Generation Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Simulation Based Test Generation for Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Debesh Kumar Das , Chiiho Sano , Takahiro Mihara , Hideo Fujiwara Test Generation for Acyclic Sequential Circuits with Hold Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Pronath , Volker Gloeckel , Helmut E. Graeb A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sudip Chakrabarti , Abhijit Chatterjee Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lode Nachtergaele , Vivek Tiwari , Nikil D. Dutt System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej J. Strojwas Design-Manufacturing Interface for 0.13 Micron and Below. [Citation Graph (0, 0)][DBLP ] Conf ] 