Conferences in DBLP
Peter Koo , Fabrizio Lombardi , Donatella Sciuto A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Shinichiro Haruyama , D. F. Wong , Donald S. Fussell Topological Routing Using Geometric Information. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Cai , D. F. Wong An Optimal Channel Pin Assignment Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Grodstein , Jengwei Pan , William J. Grundmann , Bruce Gieseke , Yao-Tsung Yen Constraint Identification for Timing Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Grodstein , Jim Montanaro , Susanne Marino Race Detection for Two-Phase Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Habib Youssef , Eugene Shragowitz Timing Constraints for Correct Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer An Automata-Theoretic Approach to Behavioral Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Eduard Cerny , C. Mauras Tautology Checking Using Cross-Controllability and Cross-Observability Relations. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita , Yusuke Matsunaga , Takeo Kakuda Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] G. Meixner , Ulrich Lauther A New Global Router Based on a Flow Model and Linear Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Somchai Prasitjutrakul , William J. Kubitz A Timing-Driven Global Router for Custom Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wei-Ming Dai , Raymond Kong , Jeffrey Jue Rubber Band Routing and Dynamic Data Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Kaoru Kawamura , T. Shindo , Toshiyuki Shibuya , H. Miwatari , Y. Ohki Touch and Cross Router. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Razdan , Gabriel P. Bischoff , Ernst G. Ulrich Exploitation of Periodicity in Logic Simulation of Synchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Robert B. Mueller-Thuns , Daniel G. Saab , Prithviraj Banerjee , Jacob A. Abraham SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] E. Vandris , Gerald E. Sobelman Fast Switch-Level Fault Simulation Using Functional Fault Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Fabio Somenzi Minimization of Symbolic Relations. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Srinivasan , Timothy Kam , Sharad Malik , Robert K. Brayton Algorithms for Discrete Function Manipulation. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram , Malgorzata Marek-Sadowska , Ernest S. Kuh Floorplanning with Pin Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Chong-Min Kyung , Peter V. Kraus , Dieter A. Mlynski Diffusion - An Analytic Procedure Applied to Macro Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Gopalakrishnan Vijayan , Ren-Song Tsay Floorplanning by Topological Constraint Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Styblinski Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Linda Milor , Alberto L. Sangiovanni-Vincentelli Computing Parametric Yield Accurately and Efficiently. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , Stephen W. Director Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Jean Christophe Madre A Unified Framework for the Formal Verification of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hervé J. Touati , Hamid Savoj , Bill Lin , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Implicit State Enumeration of Finite State Machines Using BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunwoo Cho , Gary D. Hachtel , Seh-Woong Jeong , Bernard Plessier , Eric M. Schwarz , Fabio Somenzi ATPG Aspects of FSM Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Masako Murofushi , Masaaki Yamada , Takashi Mitsuhashi FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Allen C.-H. Wu , Daniel Gajski Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Lengauer , Rolf Müller A Robust Framework for Hierarchical Floorplanning with Integrated Global Wiring. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Herrigel GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Cheng Ju , Fred L. Yang , Resve A. Saleh Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Visweswariah , Peter Feldmann , Ronald A. Rohrer Incorporation of Inductors in Piecewise Approximate Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Rui Wang , Omar Wing Analysis of VLSI Microconductor Systems by Bi-Level Waveform Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Charles A. Zukowski , George Gristede , Albert E. Ruehli Measuring Error Propagation in Waveform Relaxation Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ohmura , Hiroto Yasuura , Keikichi Tamaru Extraction of Functional Information from Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Se-Kyoung Hong , In-Cheol Park , Chong-Min Kyung An O(n 3 logn )-Heuristic for Microcode Bit Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Vanbekbergen , Francky Catthoor , Gert Goossens , Hugo De Man Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Wallace , Mandalagiri S. Chandrasekhar High-Level Delay Estimation for Technology-Independent Logic Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Yoichi Shiraishi , Mitsuyuki Kimura , Kazuhiko Kobayashi , Tetsuro Hino , Miki Seriuchi , Manabu Kusaoke A High-Packing Density Module Generator for Bipolar Analog LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Umakanta Choudhury , Alberto L. Sangiovanni-Vincentelli Constraint-Based Channel Routing for Analog and Mixed Analog/Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Malavasi , Umakanta Choudhury , Alberto L. Sangiovanni-Vincentelli A Routing Methodology for Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Elke A. Rundensteiner , Daniel Gajski , Lubomir Bic The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Jain MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Giovanni De Micheli Partitioning of Functional Models of Synchronous Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Mahlstedt , Torsten Grüning , Cengiz Özcan , Wilfried Daehn Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Jing-Yang Jou A Single-State-Transition Fault Model for Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Hung Chen , Jacob A. Abraham Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna P. Belkhale , Prithviraj Banerjee A Parallel Algorithm for Hierarchical Circuit Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Hirotoshi Sawada A Hierarchical Circuit Extractor Based on New Cell Overlap Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Grundmann , Yao-Tsung Yen XREF/COUPLING: Capacitive Coupling Error Checker. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Claude Dufourd , Jean-François Naviner , Francis Jutand Preform: A Process Independent Symbolic Layout System. [Citation Graph (0, 0)][DBLP ] Conf ] D. L. Springer , Donald E. Thomas Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys , Mohamed I. Elmasry A Global Optimization Approach for Architectural Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Nestor , Ganesh Krishnamoorthy SALSA: A New Approach to Scheduling with Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Susana Stoica A Hierarchical Approach for Testing Large Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Geilert , Jürgen Alt , Michael Zimmermann On the Efficiency of the Transition Fault Model for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Scott H. Robinson , John Paul Shen Evaluation and Synthesis of Self-Monitoring State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Mao , Ravi K. Gulati , Deepak K. Goel , Michael D. Ciletti QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Gani Jusuf , Paul R. Gray , Alberto L. Sangiovanni-Vincentelli CADICS - Cyclic Analog-to-Digital Converter Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dale E. Hocevar , Rajeev Arora , Uttiya Dasgupta , Sattam Dasgupta , Nagaraj Subramanyam , Sham Kashyap A Usable Circuit Optimizer for Designers. [Citation Graph (0, 0)][DBLP ] Conf ] Linda Milor , Alberto L. Sangiovanni-Vincentelli Optimal Test Set Design for Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David Knapp Feedback-Driven Datapath Optimization in Fasolt. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Ewering Automatic High Level Syntesis of Partitioned Busses. [Citation Graph (0, 0)][DBLP ] Conf ] Fur-Shing Tsai , Yu-Chin Hsu Data Path Construction and Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Kee Sup Kim , Charles R. Kime Partial Scan by Use of Empirical Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Tsu-Wei Ku , Wei-Kong Chia Test Vector Minimization During Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Ho Lee , Sudhakar M. Reddy On Determining Scan Flip-Flops in Partial-Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. B. Jackson , Arvind Srinivasan , Ernest S. Kuh A Fast Algorithm for Performance-Driven Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Mayrhofer , Ulrich Lauther Congestion-Driven Placement Using a New Multi-Partitioning Heuristic. [Citation Graph (0, 0)][DBLP ] Conf ] William Swartz , Carl Sechen New Algorithms for the Placement and Routing of Macro Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Cheryl Harkness , Daniel P. Lopresti VLSI Placement Using Uncertain Costs. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Allen , Douglas Rosenthal , Kenneth W. Fiduk Distributed Methodology Management for Design-in-the-Large. [Citation Graph (0, 0)][DBLP ] Conf ] Felix Bretschneider , Christa Kopf , Helmut Lagger , Arding Hsu , Elizabeth Wei Knowledge Based Design Flow Management. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Miyazaki , Tamio Hoshino , Makoto Endo A CAD Process Scheduling Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Tzi-cker Chiueh , Randy H. Katz A History Model for Managing the VLSI Design Process. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer , Babak Salimi On the Diagnostic Resolution of Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] André Ivanov , Yervant Zorian Computing the Error Escape Probability in Count-Based Compaction Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Paul G. Ryan , W. Kent Fuchs Partial Detectability Profiles. [Citation Graph (0, 0)][DBLP ] Conf ] Ikuo Harada , Hitoshi Kitazawa , Takao Kaneko A Routing System for Mixed A/D Standard Cell LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Dean Brown , Jonathan Rose , Zvonko G. Vranesic A Detailed Router for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Akihiko Hanafusa , Yasuhiro Yamashita , Mitsuru Yasuda Three-Dimensional Routing for Multilayer Ceramic Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Hansruedi Heeb , Albert E. Ruehli , J. Janak , Shahrokh Daijavad Simulating Electromagnetic Radiation of Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Jagau SIMCURRENT: An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuf Leblebici , Sung-Mo Kang An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Matsunaga , Masahiro Fujita , Takeo Kakuda Multi-Level Logic Minimization Across Latch Boundaries. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Malik , Kanwar Jit Singh , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Performance Optimization of Pipelined Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Hervé J. Touati , A. Richard Newton Don't Care Minimization of Multi-Level Sequential Logic Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Edahiro A Clock Net Reassignment Algorithm Usign Voronoi Diagram. [Citation Graph (0, 0)][DBLP ] Conf ] Jan-Ming Ho , Majid Sarrafzadeh , Atsushi Suzuki An Exact Algorithm for Single-Layer Wire-Length Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Gabriel Robins A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Hai Chao , Yu-Chin Hsu Rectilinear Steiner Tree Construction by Local and Global Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Trotter , Prathima Agrawal Circuit Simulation Algorithms on a Distributed Memory Multiprocessor System. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Miguel Silveira , Andrew Lumsdaine , Jacob White Parallel Simulation Algorithms for Grid-Based Analog Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Kartikeya Mayaram , Ping Yang , Jue-Hsien Chern , Richard Burch , Lawrence A. Arledge Jr. , Paul F. Cox A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Trotter , Prathima Agrawal Fast Overlapped Scattered Array Storage Schemes for Sparse Matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Bryan , Srinivas Devadas , Kurt Keutzer Testability-Preserving Circuit Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Saldanha , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli , Kwang-Ting Cheng Timing Optimization with Testability Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Heh-Tyan Liaw , Jia-Horng Tsaih , Chen-Shang Lin Efficient Automatic Diagnosis of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Tomita , Hong-Hai Jiang , Tamotsu Yamamoto , Yoshihiro Hayashi An Algorithm for Locating Logic Design Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Jukka Lahti , Jorma Kivelä Logic Compilation from Graphical Dependency Notation. [Citation Graph (0, 0)][DBLP ] Conf ] Nishit P. Parikh , Chi-Yuan Lo , Anoop Singhal , Kwok W. Wu HS: A Hierarchical Search Package for CAD Data. [Citation Graph (0, 0)][DBLP ] Conf ] Peter van den Hamer , Menno Treffers A Data Flow Based Architecture for CAD Frameworks. [Citation Graph (0, 0)][DBLP ] Conf ] Ibrahim N. Hajj An Algebra for Switch-Level Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Rajiv Gupta , Melvin A. Breuer A New Method for Assigning Signal Flow Directions to MOS Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Srimat T. Chakradhar Logic Simulation and Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Damiani , Giovanni De Micheli Observability Don't Care Sets and Boolean Relations. [Citation Graph (0, 0)][DBLP ] Conf ] F. Crowet , Marc Davio , C. Dierieck , J. Durieu , G. Louis , Chantal Ykman-Couvreur PHIFACT, a Boolean Preprocessor for Multi-Level Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jagadeesh Vasudevamurthy , Janusz Rajski A Method for Concurrent Decomposition and Factorization of Boolean Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Chuen Wei , Chung-Kuan Cheng A Two-Level Two-Way Partitioning Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jörn Garbers , Hans Jürgen Prömel , Angelika Steger Finding Clusters in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] T. W. Her , D. F. Wong , T. H. Freeman Optimal Orientations of Transistor Chains. [Citation Graph (0, 0)][DBLP ] Conf ] John Conway , Gerard Beenker A New Template Based Approach to Module Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoli Huang , Vivek Raghavan , Ronald A. Rohrer AWEsim: A Program for the Efficient Analysis of Linear(ized) Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John Y. Lee , Xiaoli Huang , Ronald A. Rohrer Efficient Pole Zero Sensitivity Calculation in AWE. [Citation Graph (0, 0)][DBLP ] Conf ] Tak K. Tang , Michel S. Nakhla Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas R. Holberg , Santanu Dutta , Lawrence T. Pillage DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Karem A. Sakallah , Trevor N. Mudge , Kunle Olukotun check Tc and min Tc : Timing Verification and Optimal Clocking of Synchronous Digtal Circuits.Citation Graph (0, 0)][DBLP ] Conf ] Kaname Kuroki , Nobuyoshi Nomizu , Shigenobu Suzuki , Kazutoshi Takahashi A Framework Environment for Logic Design Support System. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Lavagno , Sharad Malik , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Nagoya , Yukihiro Nakamura , Kiyoshi Oguri , Ryo Nomura Multi-Level Optimization for Large Scale ASICS. [Citation Graph (0, 0)][DBLP ] Conf ] 