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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
2001 (conf/iccad/2001)

  1. Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen
    Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:- [Conf]
  2. Murali Kudlugi, Charles Selvidge, Russell Tessier
    Static Scheduling of Multi-Domain Memories For Functional Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:2-9 [Conf]
  3. Scott A. Taylor, Carl Ramey, Craig Barner, David Asher
    A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:10-17 [Conf]
  4. Jinsheng Xu, Moon-Jung Chung
    Predicting the Performance of Synchronous Discrete Event Simulation Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:18-0 [Conf]
  5. Tony Givargis, Frank Vahid, Jörg Henkel
    System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:25-30 [Conf]
  6. Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere
    System Level Design with Spade: an M-JPEG Case Study. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:31-38 [Conf]
  7. Gokhan Memik, William H. Mangione-Smith, Wendong Hu
    NetBench: A Benchmarking Suite for Network Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:39-0 [Conf]
  8. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
    Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:44-48 [Conf]
  9. Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
    A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:49-56 [Conf]
  10. Bret M. Victor, Kurt Keutzer
    Bus Encoding to Prevent Crosstalk Delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:57-0 [Conf]
  11. Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
    Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:65-69 [Conf]
  12. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:70-74 [Conf]
  13. Yu-Min Lee, Charlie Chung-Ping Chen
    Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:75-0 [Conf]
  14. Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
    Sequential SPFDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:84-90 [Conf]
  15. Enrique San Millán, Luis Entrena, José Alberto Espejo
    On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:91-94 [Conf]
  16. Ingmar Neumann, Wolfgang Kunz
    Placement Driven Retiming with a Coupled Edge Timing Model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:95-102 [Conf]
  17. Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
    Solution of Parallel Language Equations for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:103-0 [Conf]
  18. Cagdas Akturan, Margarida F. Jacome
    CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:112-118 [Conf]
  19. Prabhat Jain, Srinivas Devadas, Daniel W. Engels, Larry Rudolph
    Software-Assisted Cache Replacement Mechanisms for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:119-126 [Conf]
  20. Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Instruction Generation for Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:127-0 [Conf]
  21. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
    Interconnect Resource-Aware Placement for Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:132-136 [Conf]
  22. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:137-143 [Conf]
  23. Vinay Verma, Shantanu Dutt
    A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:144-0 [Conf]
  24. Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:153-157 [Conf]
  25. Kaustav Banerjee, Amit Mehrotra
    Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:158-164 [Conf]
  26. TingYen Chiang, Kaustav Banerjee, Krishna Saraswat
    Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:165-0 [Conf]
  27. Andreas Kuehlmann, Robert W. Dutton, Paul D. Franzon, Seth Copen Goldstein, Philip Luekes, Eric Parker, Thomas N. Theis
    Will Nanotechnology Change the Way We Design and Verify Systems? (Panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:174- [Conf]
  28. Jason Baumgartner, Andreas Kuehlmann
    Min-Area Retiming on Dynamic Circuit Structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:176-182 [Conf]
  29. Dominik Stoffel, Wolfgang Kunz
    Verification of Integer Multipliers on the Arithmetic Bit Level. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:183-189 [Conf]
  30. Ying-Tsai Chang, Kwang-Ting Cheng
    Induction-Based Gate-Level Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:190-0 [Conf]
  31. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    An Assembly-Level Execution-Time Model for Pipelined Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:195-200 [Conf]
  32. Mahmut T. Kandemir, Ugur Sezer, Victor Delaluz
    Improving Memory Energy Using Access Pattern Classification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:201-206 [Conf]
  33. Radu Marculescu, Amit Nandi, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:207-0 [Conf]
  34. Thomas Kutzschebauch, Leon Stok
    Congestion Aware Layout Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:216-223 [Conf]
  35. Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli
    Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:224-231 [Conf]
  36. Hua Xiang, Xiaoping Tang, D. F. Wong
    An Algorithm for Simultaneous Pin Assignment and Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:232-0 [Conf]
  37. Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob White
    Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:240-244 [Conf]
  38. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    A Convex Programming Approach to Positive Real Rational Approximation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:245-251 [Conf]
  39. Michal Rewienski, Jacob White
    A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:252-0 [Conf]
  40. Niraj K. Jha
    Low Power System Scheduling and Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:259-263 [Conf]
  41. Lothar Thiele
    Integral Design Representations for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:264- [Conf]
  42. Diederik Verkest, Peng Yang, Chun Wong, Paul Marchal
    Optimisation Problems for Dynamic Concurrent Task-Based Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:265-0 [Conf]
  43. Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik
    Efficient Conflict Driven Learning in Boolean Satisfiability Solver. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:279-285 [Conf]
  44. Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
    Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:286-292 [Conf]
  45. Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang
    Non-linear Quantification Scheduling in Image Computation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:293-0 [Conf]
  46. Armita Peymandoust, Giovanni De Micheli
    Symbolic Algebra and Timing Driven Data-flow Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:300-305 [Conf]
  47. Diana Marculescu, Anoop Iyer
    Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:306-313 [Conf]
  48. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    A System for Synthesizing Optimized FPGA Hardware from MATLAB. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:314-319 [Conf]
  49. Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi
    Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:320-0 [Conf]
  50. James D. Z. Ma, Lei He
    Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:327-332 [Conf]
  51. Haihua Su, Sachin S. Sapatnekar
    Hybrid Structured Clock Network Construction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:333-336 [Conf]
  52. Yonghee Im, Kaushik Roy
    CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:337-0 [Conf]
  53. Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich
    The Sizing Rules Method for Analog Integrated Circuit Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:343-349 [Conf]
  54. Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley
    ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:350-357 [Conf]
  55. Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    A Layout-Aware Synthesis Methodology for RF Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:358-0 [Conf]
  56. Seiji Kajihara, Kohei Miyase
    On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:364-369 [Conf]
  57. Chen Wang, Irith Pomeranz, Sudhakar M. Reddy
    REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:370-374 [Conf]
  58. Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota
    Crosstalk Fault Detection by Dynamic Idd. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:375-0 [Conf]
  59. Jianwen Zhu, Edward S. Rogers Sr.
    Color Permutation: An Iterative Algorithm for Memory Packing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:380-383 [Conf]
  60. Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess
    Constraint Satisfaction for Relative Location Assignment and Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:384-390 [Conf]
  61. Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    A Super-Scheduler for Embedded Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:391-0 [Conf]
  62. Jason Cong, Jie Fang, Yan Zhang VI
    Multilevel Approach to Full-Chip Gridless Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:396-403 [Conf]
  63. Fan Mo, Abdallah Tabbara, Robert K. Brayton
    A Force-Directed Maze Router. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:404-407 [Conf]
  64. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:408-0 [Conf]
  65. Joe Kanapka, Jacob White
    Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:417-423 [Conf]
  66. Minqing Liu, Tiejun Yu, Wayne Wei-Ming Dai
    Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:424-429 [Conf]
  67. Joel R. Phillips, Luis Miguel Silveira
    Simulation Approaches for Strongly Coupled Interconnect Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:430-0 [Conf]
  68. Jan Hlavicka, Petr Fiser
    BOOM - A Heuristic Boolean Minimizer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:439-442 [Conf]
  69. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Faster SAT and Smaller BDDs via Common Function Structure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:443-448 [Conf]
  70. Rupesh S. Shelar, Sachin S. Sapatnekar
    Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:449-452 [Conf]
  71. Jennifer L. Wong, Farinaz Koushanfar, Seapahn Meguerdichian, Miodrag Potkonjak
    A Probabilistic Constructive Approach to Optimization Problems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:453-0 [Conf]
  72. Amit Sinha, Anantha Chandrakasan
    Energy Efficient Real-Time Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:458-470 [Conf]
  73. Hongchao (Stephanie) Liu, Xiaobo Hu
    Efficient Performance Estimation for General Real-Time Task Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:464-470 [Conf]
  74. Felice Balarin
    Stars in VCC: Complementing Simulation with Worst-Case Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:471-0 [Conf]
  75. Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
    Multigrid-Like Technique for Power Grid Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:480-487 [Conf]
  76. Daler N. Rakhmatov, Sarma B. K. Vrudhula
    An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:488-493 [Conf]
  77. José Luis Rosselló, Jaume Segura
    Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:494-0 [Conf]
  78. Clayton B. McDonald, Randal E. Bryant
    A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:501-506 [Conf]
  79. Jin-fuw Lee, Daniel L. Ostapko, Jeffery Soreff, C. K. Wong
    On the Signal Bounding Problem in Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:507-514 [Conf]
  80. Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
    False-Noise Analysis using Logic Implications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:515-0 [Conf]
  81. Erik Larsson, Zebo Peng, Gunnar Carlsson
    The Design and Optimization of SOC Test Solutions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:523-530 [Conf]
  82. Donald B. Shaw, Dhamin Al-Khalili, Come Rozon
    Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:531-536 [Conf]
  83. Kaijie Wu, Ramesh Karri
    Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:537-0 [Conf]
  84. Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
    Transient Power Management Through High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:545-552 [Conf]
  85. Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
    An Integrated Data Path Optimization for Low Power Based on Network Flow Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:553-559 [Conf]
  86. Gang Qu
    What is the Limit of Energy Saving by Dynamic Voltage Scaling? [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:560-0 [Conf]
  87. Oluf Faroe, David Pisinger, Martin Zachariasen
    Local Search for Final Placement in VLSI Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:565-572 [Conf]
  88. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion Reduction During Placement Based on Integer Programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:573-576 [Conf]
  89. Prakash Gopalakrishnan, Rob A. Rutenbar
    Direct Transistor-Level Layout for Digital Blocks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:577-0 [Conf]
  90. Payam Heydari, Massoud Pedram
    Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:586-591 [Conf]
  91. Zhenhai Zhu, Jingfang Huang, Ben Song, Jacob White
    Improving the Robustness of a Surface Integral Formulation for Wideband Impendance Extraction of 3D Structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:592-597 [Conf]
  92. Steven C. Chan, Kenneth L. Shepard
    Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:598-0 [Conf]
  93. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    Single-Pass Redundancy Addition and Removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:606-609 [Conf]
  94. Jovanka Ciric, Carl Sechen
    Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:610-617 [Conf]
  95. Robert K. Brayton
    Compatible Observability Don't Cares Revisited. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:618-0 [Conf]
  96. Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
    A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:625-630 [Conf]
  97. Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
    Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:631-634 [Conf]
  98. Sri Parameswaran, Jörg Henkel
    I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:635-0 [Conf]
  99. Sudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu
    IC Power Distribution Challenges. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:643-650 [Conf]
  100. Shen Lin, Norman Chang
    Challenges in Power-Ground Integrity. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:651-0 [Conf]
  101. Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
    Automatic Hierarchical Design: Fantasy or Reality? (Panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:656-0 [Conf]
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