Conferences in DBLP
Soren Hein , Vijay Nagasamy , Bernhard Rohfleisch , Christoforos E. Kozyrakis , Nikil D. Dutt , Francky Catthoor Embedded memories in system design - from technology to systems architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Serge Hustin , Miodrag Potkonjak , Eric Verhulst , Wayne Wolf Real-time operating systems for embedded computing. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Jacob A. Abraham , Yervant Zorian High-level design validation and test. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Restle , Joel R. Phillips , Ibrahim M. Elfadel Interconnect in high speed designs: problems, methodologies and tools. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken , Jason Cong , Randy Harr , Kenneth L. Shepard , Wayne Wolf How will CAD handle billion-transistor systems? (panel). [Citation Graph (0, 0)][DBLP ] Conf ] Tong Li , Ching-Han Tsai , Sung-Mo Kang Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress. [Citation Graph (0, 0)][DBLP ] Conf ] Tuyen V. Nguyen , Anirudh Devgan , Ali Sadigh Simulation of coupling capacitances using matrix partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Lin , Emrah Acar , Lawrence T. Pileggi h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. [Citation Graph (0, 0)][DBLP ] Conf ] Wilsin Gosti , Amit Narayan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Wireplanning in logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Wen Chang , Jai-Ming Lin , D. F. Wong Graph matching-based algorithms for FPGA segmentation design. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Songjie Xu Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Ken Hines , Kurt Partridge , Gaetano Borriello Control generation for embedded systems based on composition of modal processes. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Ziegenbein , Kai Richter , Rolf Ernst , Jürgen Teich , Lothar Thiele Representation of process mode correlation for scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Dick , Niraj K. Jha CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Pendurkar , Abhijit Chatterjee , Yervant Zorian Synthesis of BIST hardware for performance testing of MCM interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Jih-Jeen Chen , Cheng-Hua Huang Using a single input to support multiple scan chains. [Citation Graph (0, 0)][DBLP ] Conf ] Frank F. Hsu , Janak H. Patel High-level variable selection for partial-scan implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Qingjian Yu , Janet Meiling Wang , Ernest S. Kuh Multipoint moment matching model for multiport distributed interconnect networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury Reduced-order modelling of linear time-varying systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joel R. Phillips Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors. [Citation Graph (0, 0)][DBLP ] Conf ] Subarnarekha Sinha , Robert K. Brayton Implementation and use of SPFDs in optimizing Boolean networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shin-ichi Minato , Giovanni De Micheli Finding all simple disjunctive decompositions using irredundant sum-of-products forms. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Matsunaga On accelerating pattern matching for technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Saxena , C. L. Liu A performance-driven layer assignment algorithm for multiple interconnect trees. [Citation Graph (0, 0)][DBLP ] Conf ] Avaneendra Gupta , John P. Hayes Optimal 2-D cell layout with integrated transistor folding. [Citation Graph (0, 0)][DBLP ] Conf ] Tzu-Chieh Tien , Hsiao-Pin Su , Yu-Wen Tsay , Yih-Chih Chou , Youn-Long Lin Integrating logic retiming and register placement. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Bommu , Srimat T. Chakradhar , Kiran B. Doreswamy Static compaction using overlapped restoration and segment pruning. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Boppana , W. Kent Fuchs Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao A fast, accurate, and non-statistical method for fault coverage estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark M. Gourary , Sergey L. Ulyanov , Michael M. Zharov , Sergey G. Rusakov Simulation of high-Q oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Demir Phase noise in oscillators: DAEs and colored noise sources. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Kapur , David E. Long High-order Nyström schemes for efficient 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP ] Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Signature hiding techniques for FPGA intellectual property protection. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Miodrag Potkonjak Analysis of watermarking techniques for graph coloring problem. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Yean-Yow Hwang , Miodrag Potkonjak , Jason Cong Intellectual property protection by watermarking combinational logic synthesis solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury , Alper Demir Estimating noise in RF systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Sylvester , Kurt Keutzer Getting to the bottom of deep submicron. [Citation Graph (0, 0)][DBLP ] Conf ] Paul D. Gross , Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi Determination of worst-case aggressor alignment for delay calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew R. Conn , Ruud A. Haring , Chandramouli Visweswariah Noise considerations in circuit optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rajamohana Hegde , Naresh R. Shanbhag Energy-efficiency in presence of deep submicron noise. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Ferrandi , Alberto Macii , Enrico Macii , Massimo Poncino , Riccardo Scarsi , Fabio Somenzi Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tyler Thorp , Gin Yee , Carl Sechen Domino logic synthesis using complex static gates. [Citation Graph (0, 0)][DBLP ] Conf ] Min Zhao , Sachin S. Sapatnekar Technology mapping for domino logic. [Citation Graph (0, 0)][DBLP ] Conf ] Fung Yu Young , D. F. Wong Slicing floorplans with pre-placed modules. [Citation Graph (0, 0)][DBLP ] Conf ] Maggie Zhiwei Kang , Wayne Wei-Ming Dai Arbitrary rectilinear block packing based on sequence pair. [Citation Graph (0, 0)][DBLP ] Conf ] Keishi Sakanushi , Shigetoshi Nakatake , Yoji Kajitani The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla , Premachandran R. Menon On primitive fault test generation in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ilker Hamzaoglu , Janak H. Patel Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su A linear optimal test generation algorithm for interconnect testing. [Citation Graph (0, 0)][DBLP ] Conf ] Maria del Mar Hershenson , Stephen P. Boyd , Thomas H. Lee GPCAD: a tool for CMOS op-amp synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Francky Leyn , Georges G. E. Gielen , Willy M. C. Sansen An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Geert Debyser , Georges G. E. Gielen Efficient analog circuit synthesis with simultaneous yield and robustness optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Iyer , Maciej J. Ciesielski Reencoding for cycle-time minimization under fixed encoding length. [Citation Graph (0, 0)][DBLP ] Conf ] Soha Hassoun , Carl Ebeling Using precomputation in architecture and logic resynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Alexander Taubin , Alexandre Yakovlev Lazy transition systems: application to timing optimization of asynchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Chowdhary , Sudhakar Kale , Phani K. Saripella , Naresh Sehgal , Rajesh K. Gupta A general approach for regularity extraction in datapath circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luc Séméria , Giovanni De Micheli SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C. [Citation Graph (0, 0)][DBLP ] Conf ] Chunho Lee , Miodrag Potkonjak A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] In-Ho Moon , Jae-Young Jang , Gary D. Hachtel , Fabio Somenzi , Jun Yuan , Carl Pixley Approximate reachability don't cares for CTL model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gila Kamhi , Limor Fix Adaptive variable reordering for symbolic model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar G. Govindaraju , David L. Dill Verification by approximate forward and backward reachability. [Citation Graph (0, 0)][DBLP ] Conf ] Ravindranath Naiknaware , Terri S. Fiez CMOS analog circuit stack generation with matching constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Sam D. Huynh , Seongwon Kim , Mani Soma , Jinyan Zhang Testability analysis and multi-frequency ATPG for analog circuits and systems. [Citation Graph (0, 0)][DBLP ] Conf ] Junwei Hou , Abhijit Chatterjee CONCERT: a concurrent transient fault simulator for nonlinear analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhiro Nakamura , Kazuyoshi Takagi , Shinji Kimura , Katsumasa Watanabe Waiting false path analysis of sequential logic circuits for performance optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Marios C. Papaefthymiou Asymptotically efficient retiming under setup and hold constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev K. Ranjan , Vigyan Singhal , Fabio Somenzi , Robert K. Brayton On the optimization power of retiming and resynthesis transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Chau-Shen Chen , TingTing Hwang , C. L. Liu Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Tarafdar , Miriam Leeser , Zixin Yin Integrating floorplanning in data-transfer based high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Shigetoshi Nakatake , Keishi Sakanushi , Yoji Kajitani , Masahiro Kawakita The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yih-Chih Chou , Youn-Long Lin A graph-partitioning-based approach for multi-layer constrained via minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Yanbing Li , Wayne Wolf Hardware/software co-synthesis with memory hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] Ross B. Ortega , Gaetano Borriello Communication synthesis for distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kayhan Küçükçakar Analysis of emerging core-based design lifecycle. [Citation Graph (0, 0)][DBLP ] Conf ] Enno Wein Core integration: overview and challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Resve A. Saleh , David Overhauser , Sandy Taylor Full-chip verification of UDSM designs. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Luca Benini Node sampling: a robust RTL power modeling approach. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanping Chen , Kaushik Roy , Edwin K. P. Chong Estimation of power sensitivity in sequential circuits with power macromodeling application. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Pinar , C. L. Liu Power invariant vector sequence compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Haynal , Forrest Brewer Efficient encoding for exact symbolic automata-based scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge M. Pena , Arlindo L. Oliveira A new algorithm for the reduction of incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Wang , Sarma B. K. Vrudhula Static power optimization of deep submicron CMOS circuits for dual VT technology. [Citation Graph (0, 0)][DBLP ] Conf ] Huiqun Liu , D. F. Wong Network flow based circuit partitioning for time-multiplexed FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sverre Wichlund On multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Sung Kyu Lim Multiway partitioning with pairwise movement. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Subhrajit Bhattacharya , Anand Raghunathan , Akira Mukaiyama Verification of RTL generated from scheduled behavior in a high-level synthesis flow. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Miodrag Potkonjak , Lisa Guerra Functional debugging of systems-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Hsin Ho , Adrian J. Isles , Timothy Kam Formal verification of pipeline control using controlled token nets and abstract interpretation. [Citation Graph (0, 0)][DBLP ] Conf ] Akio Hirata , Hidetoshi Onodera , Keikichi Tamaru Proposal of a timing model for CMOS logic gates driving a CRC load. [Citation Graph (0, 0)][DBLP ] Conf ] Frederik Beeftink , Prabhakar Kudva , David S. Kung , Leon Stok Gate-size selection for standard cell libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Pasquale Cocchini , Massoud Pedram , Gianluca Piccinini , Maurizio Zamboni Fanout optimization under a submicron transistor-level delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Gagan Hasteer , Anmol Mathur , Prithviraj Banerjee Efficient equivalence checking of multi-phase designs using retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch , Vigyan Singhal Robust latch mapping for combinational equivalence checking. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch , Vigyan Singhal Tight integration of combinational verification methods. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Wim F. J. Verhaegh , Emile H. L. Aarts , Paul C. N. van Gorp Period assignment in multidimensional periodic scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] M. Narasimhan , J. Ramanujam Improving the computational performance of ILP-based problems. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Miodrag Potkonjak Techniques for energy minimization of communication pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Roy , Harm Arts , Prithviraj Banerjee PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis. [Citation Graph (0, 0)][DBLP ] Conf ] Efstathios D. Kyriakis-Bitzaros , Spiridon Nikolaidis , Anna Tatsaki Accurate calculation of bit-level transition activity using word-level statistics and entropy function. [Citation Graph (0, 0)][DBLP ] Conf ] Youxin Gao , D. F. Wong Shaping a VLSI wire to minimize delay using transmission line model. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ping Chen , Chris C. N. Chu , D. F. Wong Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Salek , Jinan Lou , Massoud Pedram A simultaneous routing tree construction and fanout optimization algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jawahar Jain , William Adams , Masahiro Fujita Sampling schemes for computing OBDD variable orderings. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Long The design of a cache-friendly BDD library. [Citation Graph (0, 0)][DBLP ] Conf ] Justin E. Harlow III , Franc Brglez Design of experiments in BDD variable ordering: lessons learned. [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Miodrag Potkonjak , Mani B. Srivastava On-line scheduling of hard real-time tasks on variable voltage processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey Transforming control-flow intensive designs to facilitate power management. [Citation Graph (0, 0)][DBLP ] Conf ] Hoon Choi , Seung Ho Hwang , Chong-Min Kyung , In-Cheol Park Synthesis of application specific instructions for embedded DSP software. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Scholl , Bernd Becker , Thomas M. Weis Word-level decision diagrams, WLCDs and division. [Citation Graph (0, 0)][DBLP ] Conf ] James Smith , Giovanni De Micheli Polynomial methods for component matching and verification. [Citation Graph (0, 0)][DBLP ] Conf ] Karsten Strehl , Lothar Thiele Symbolic model checking of process networks using interval diagram techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Gaetano Borriello , Luciano Lavagno , Ross B. Ortega Interface synthesis: a vertical slice from digital logic to software components. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alessandro Bogliolo , Giovanni De Micheli Dynamic power management of electronic systems. [Citation Graph (0, 0)][DBLP ] Conf ] 