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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
1998 (conf/iccad/1998)

  1. Soren Hein, Vijay Nagasamy, Bernhard Rohfleisch, Christoforos E. Kozyrakis, Nikil D. Dutt, Francky Catthoor
    Embedded memories in system design - from technology to systems architecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:1- [Conf]
  2. Serge Hustin, Miodrag Potkonjak, Eric Verhulst, Wayne Wolf
    Real-time operating systems for embedded computing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:2- [Conf]
  3. Sujit Dey, Jacob A. Abraham, Yervant Zorian
    High-level design validation and test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:3- [Conf]
  4. Phillip Restle, Joel R. Phillips, Ibrahim M. Elfadel
    Interconnect in high speed designs: problems, methodologies and tools. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:4- [Conf]
  5. Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf
    How will CAD handle billion-transistor systems? (panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:5- [Conf]
  6. Tong Li, Ching-Han Tsai, Sung-Mo Kang
    Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:6-11 [Conf]
  7. Tuyen V. Nguyen, Anirudh Devgan, Ali Sadigh
    Simulation of coupling capacitances using matrix partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:12-18 [Conf]
  8. Tao Lin, Emrah Acar, Lawrence T. Pileggi
    h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:19-25 [Conf]
  9. Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Wireplanning in logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:26-33 [Conf]
  10. Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
    Graph matching-based algorithms for FPGA segmentation design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:34-39 [Conf]
  11. Jason Cong, Songjie Xu
    Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:40-44 [Conf]
  12. Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Borriello
    Control generation for embedded systems based on composition of modal processes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:46-53 [Conf]
  13. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele
    Representation of process mode correlation for scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:54-61 [Conf]
  14. Robert P. Dick, Niraj K. Jha
    CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:62-67 [Conf]
  15. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    Synthesis of BIST hardware for performance testing of MCM interconnections. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:69-73 [Conf]
  16. Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
    Using a single input to support multiple scan chains. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:74-78 [Conf]
  17. Frank F. Hsu, Janak H. Patel
    High-level variable selection for partial-scan implementation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:79-84 [Conf]
  18. Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
    Multipoint moment matching model for multiport distributed interconnect networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:85-91 [Conf]
  19. Jaijeet S. Roychowdhury
    Reduced-order modelling of linear time-varying systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:92-95 [Conf]
  20. Joel R. Phillips
    Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:96-102 [Conf]
  21. Subarnarekha Sinha, Robert K. Brayton
    Implementation and use of SPFDs in optimizing Boolean networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:103-110 [Conf]
  22. Shin-ichi Minato, Giovanni De Micheli
    Finding all simple disjunctive decompositions using irredundant sum-of-products forms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:111-117 [Conf]
  23. Yusuke Matsunaga
    On accelerating pattern matching for technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:118-122 [Conf]
  24. Prashant Saxena, C. L. Liu
    A performance-driven layer assignment algorithm for multiple interconnect trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:124-127 [Conf]
  25. Avaneendra Gupta, John P. Hayes
    Optimal 2-D cell layout with integrated transistor folding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:128-135 [Conf]
  26. Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
    Integrating logic retiming and register placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:136-139 [Conf]
  27. Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
    Static compaction using overlapped restoration and segment pruning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:140-146 [Conf]
  28. Vamsi Boppana, W. Kent Fuchs
    Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:147-154 [Conf]
  29. Michael S. Hsiao
    A fast, accurate, and non-statistical method for fault coverage estimation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:155-161 [Conf]
  30. Mark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov
    Simulation of high-Q oscillators. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:162-169 [Conf]
  31. Alper Demir
    Phase noise in oscillators: DAEs and colored noise sources. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:170-177 [Conf]
  32. Sharad Kapur, David E. Long
    High-order Nyström schemes for efficient 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:178-185 [Conf]
  33. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Signature hiding techniques for FPGA intellectual property protection. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:186-189 [Conf]
  34. Gang Qu, Miodrag Potkonjak
    Analysis of watermarking techniques for graph coloring problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:190-193 [Conf]
  35. Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong
    Intellectual property protection by watermarking combinational logic synthesis solutions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:194-198 [Conf]
  36. Jaijeet S. Roychowdhury, Alper Demir
    Estimating noise in RF systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:199-202 [Conf]
  37. Dennis Sylvester, Kurt Keutzer
    Getting to the bottom of deep submicron. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:203-211 [Conf]
  38. Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
    Determination of worst-case aggressor alignment for delay calculation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:212-219 [Conf]
  39. Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah
    Noise considerations in circuit optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:220-227 [Conf]
  40. Rajamohana Hegde, Naresh R. Shanbhag
    Energy-efficiency in presence of deep submicron noise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:228-234 [Conf]
  41. Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi
    Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:235-241 [Conf]
  42. Tyler Thorp, Gin Yee, Carl Sechen
    Domino logic synthesis using complex static gates. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:242-247 [Conf]
  43. Min Zhao, Sachin S. Sapatnekar
    Technology mapping for domino logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:248-251 [Conf]
  44. Fung Yu Young, D. F. Wong
    Slicing floorplans with pre-placed modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:252-258 [Conf]
  45. Maggie Zhiwei Kang, Wayne Wei-Ming Dai
    Arbitrary rectilinear block packing based on sequence pair. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:259-266 [Conf]
  46. Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani
    The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:267-274 [Conf]
  47. Ramesh C. Tekumalla, Premachandran R. Menon
    On primitive fault test generation in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:275-282 [Conf]
  48. Ilker Hamzaoglu, Janak H. Patel
    Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:283-289 [Conf]
  49. Chauchin Su
    A linear optimal test generation algorithm for interconnect testing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:290-295 [Conf]
  50. Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee
    GPCAD: a tool for CMOS op-amp synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:296-303 [Conf]
  51. Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
    An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:304-307 [Conf]
  52. Geert Debyser, Georges G. E. Gielen
    Efficient analog circuit synthesis with simultaneous yield and robustness optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:308-311 [Conf]
  53. Balakrishnan Iyer, Maciej J. Ciesielski
    Reencoding for cycle-time minimization under fixed encoding length. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:312-315 [Conf]
  54. Soha Hassoun, Carl Ebeling
    Using precomputation in architecture and logic resynthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:316-323 [Conf]
  55. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems: application to timing optimization of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:324-331 [Conf]
  56. Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
    A general approach for regularity extraction in datapath circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:332-339 [Conf]
  57. Luc Séméria, Giovanni De Micheli
    SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:340-346 [Conf]
  58. Chunho Lee, Miodrag Potkonjak
    A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:347-351 [Conf]
  59. In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley
    Approximate reachability don't cares for CTL model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:351-358 [Conf]
  60. Gila Kamhi, Limor Fix
    Adaptive variable reordering for symbolic model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:359-365 [Conf]
  61. Shankar G. Govindaraju, David L. Dill
    Verification by approximate forward and backward reachability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:366-370 [Conf]
  62. Ravindranath Naiknaware, Terri S. Fiez
    CMOS analog circuit stack generation with matching constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:371-375 [Conf]
  63. Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang
    Testability analysis and multi-frequency ATPG for analog circuits and systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:376-383 [Conf]
  64. Junwei Hou, Abhijit Chatterjee
    CONCERT: a concurrent transient fault simulator for nonlinear analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:384-391 [Conf]
  65. Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe
    Waiting false path analysis of sequential logic circuits for performance optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:392-395 [Conf]
  66. Marios C. Papaefthymiou
    Asymptotically efficient retiming under setup and hold constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:396-401 [Conf]
  67. Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
    On the optimization power of retiming and resynthesis transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:402-407 [Conf]
  68. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:408-411 [Conf]
  69. Shantanu Tarafdar, Miriam Leeser, Zixin Yin
    Integrating floorplanning in data-transfer based high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:412-417 [Conf]
  70. Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
    The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:418-425 [Conf]
  71. Yih-Chih Chou, Youn-Long Lin
    A graph-partitioning-based approach for multi-layer constrained via minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:426-429 [Conf]
  72. Yanbing Li, Wayne Wolf
    Hardware/software co-synthesis with memory hierarchies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:430-436 [Conf]
  73. Ross B. Ortega, Gaetano Borriello
    Communication synthesis for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:437-444 [Conf]
  74. Kayhan Küçükçakar
    Analysis of emerging core-based design lifecycle. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:445-449 [Conf]
  75. Enno Wein
    Core integration: overview and challenges. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:450-452 [Conf]
  76. Resve A. Saleh, David Overhauser, Sandy Taylor
    Full-chip verification of UDSM designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:453-460 [Conf]
  77. Alessandro Bogliolo, Luca Benini
    Node sampling: a robust RTL power modeling approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:461-467 [Conf]
  78. Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
    Estimation of power sensitivity in sequential circuits with power macromodeling application. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:468-472 [Conf]
  79. Ali Pinar, C. L. Liu
    Power invariant vector sequence compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:473-476 [Conf]
  80. Steve Haynal, Forrest Brewer
    Efficient encoding for exact symbolic automata-based scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:477-481 [Conf]
  81. Jorge M. Pena, Arlindo L. Oliveira
    A new algorithm for the reduction of incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:482-489 [Conf]
  82. Qi Wang, Sarma B. K. Vrudhula
    Static power optimization of deep submicron CMOS circuits for dual VT technology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:490-496 [Conf]
  83. Huiqun Liu, D. F. Wong
    Network flow based circuit partitioning for time-multiplexed FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:497-504 [Conf]
  84. Sverre Wichlund
    On multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:505-511 [Conf]
  85. Jason Cong, Sung Kyu Lim
    Multiway partitioning with pairwise movement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:512-516 [Conf]
  86. Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama
    Verification of RTL generated from scheduled behavior in a high-level synthesis flow. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:517-524 [Conf]
  87. Darko Kirovski, Miodrag Potkonjak, Lisa Guerra
    Functional debugging of systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:525-528 [Conf]
  88. Pei-Hsin Ho, Adrian J. Isles, Timothy Kam
    Formal verification of pipeline control using controlled token nets and abstract interpretation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:529-536 [Conf]
  89. Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
    Proposal of a timing model for CMOS logic gates driving a CRC load. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:537-544 [Conf]
  90. Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok
    Gate-size selection for standard cell libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:545-550 [Conf]
  91. Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
    Fanout optimization under a submicron transistor-level delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:551-556 [Conf]
  92. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    Efficient equivalence checking of multi-phase designs using retiming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:557-562 [Conf]
  93. Jerry R. Burch, Vigyan Singhal
    Robust latch mapping for combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:563-569 [Conf]
  94. Jerry R. Burch, Vigyan Singhal
    Tight integration of combinational verification methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:570-576 [Conf]
  95. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:577-584 [Conf]
  96. Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp
    Period assignment in multidimensional periodic scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:585-592 [Conf]
  97. M. Narasimhan, J. Ramanujam
    Improving the computational performance of ILP-based problems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:593-596 [Conf]
  98. Gang Qu, Miodrag Potkonjak
    Techniques for energy minimization of communication pipelines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:597-600 [Conf]
  99. Sumit Roy, Harm Arts, Prithviraj Banerjee
    PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:601-606 [Conf]
  100. Efstathios D. Kyriakis-Bitzaros, Spiridon Nikolaidis, Anna Tatsaki
    Accurate calculation of bit-level transition activity using word-level statistics and entropy function. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:607-610 [Conf]
  101. Youxin Gao, D. F. Wong
    Shaping a VLSI wire to minimize delay using transmission line model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:611-616 [Conf]
  102. Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:617-624 [Conf]
  103. Amir H. Salek, Jinan Lou, Massoud Pedram
    A simultaneous routing tree construction and fanout optimization algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:625-630 [Conf]
  104. Jawahar Jain, William Adams, Masahiro Fujita
    Sampling schemes for computing OBDD variable orderings. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:631-638 [Conf]
  105. David E. Long
    The design of a cache-friendly BDD library. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:639-645 [Conf]
  106. Justin E. Harlow III, Franc Brglez
    Design of experiments in BDD variable ordering: lessons learned. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:646-652 [Conf]
  107. Inki Hong, Miodrag Potkonjak, Mani B. Srivastava
    On-line scheduling of hard real-time tasks on variable voltage processor. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:653-656 [Conf]
  108. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Transforming control-flow intensive designs to facilitate power management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:657-664 [Conf]
  109. Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park
    Synthesis of application specific instructions for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:665-671 [Conf]
  110. Christoph Scholl, Bernd Becker, Thomas M. Weis
    Word-level decision diagrams, WLCDs and division. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:672-677 [Conf]
  111. James Smith, Giovanni De Micheli
    Polynomial methods for component matching and verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:678-685 [Conf]
  112. Karsten Strehl, Lothar Thiele
    Symbolic model checking of process networks using interval diagram techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:686-692 [Conf]
  113. Gaetano Borriello, Luciano Lavagno, Ross B. Ortega
    Interface synthesis: a vertical slice from digital logic to software components. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:693-695 [Conf]
  114. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Dynamic power management of electronic systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:696-702 [Conf]
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