Conferences in DBLP
Anirudh Devgan , Leon Stok , Sandip Kundu Timing analysis and optimization: from devices to systems (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wei-Ming Dai , Howard Kalter , Rob Roy , Wayne Wolf Critical technologies and methodologies for systems-on-chips (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Mani B. Srivastava Design technology for building wireless systems (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano , Andrew Seawright , Joseph Buck Modeling and synthesis of behavior, control and dataflow (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Yirng-An Chen , Randal E. Bryant PHDD: an efficient graph representation for floating point circuit verification. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Scholl , Rolf Drechsler , Bernd Becker Functional simulation using binary decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Vuillod , Luca Benini , Giovanni De Micheli Generalized matching from theory to application. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Li , Rajesh K. Gupta Decomposition of timed decision tables and its use in presynthesis optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Hong Hwang , Allen C.-H. Wu A predictive system shutdown method for energy saving of event-driven computation. [Citation Graph (0, 0)][DBLP ] Conf ] Kyosun Kim , Ramesh Karri , Miodrag Potkonjak Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanping Chen , Kaushik Roy , Tan-Li Chou Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Effects of delay models on peak power estimation of VLSI sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan-Yu Wang , Kaushik Roy COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi PRIMA: passive reduced-order interconnect macromodeling algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ibrahim M. Elfadel , David D. Ling A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks. [Citation Graph (0, 0)][DBLP ] Conf ] Tuyen V. Nguyen , Jing Li Multipoint Padé approximation using a rational block Lanczos algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Bertacco , Maurizio Damiani The disjunctive decomposition of logic functions. [Citation Graph (0, 0)][DBLP ] Conf ] Rajat Aggarwal , Rajeev Murgai , Masahiro Fujita Speeding up technology-independent timing optimization by network partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Evguenii I. Goldberg , Luca P. Carloni , Tiziano Villa , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Negative thinking by incremental problem solving: application to unate covering. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys DSP address optimization using a minimum cost circulation technique. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith Application-driven synthesis of core-based systems. [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Miodrag Potkonjak , Ramesh Karri Power optimization using divide-and-conquer techniques for minimization of the number of operations. [Citation Graph (0, 0)][DBLP ] Conf ] Mahadevamurty Nemani , Farid N. Najm High-level area and power estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Naushik Sankarayya , Kaushik Roy , Debashis Bhattacharya Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj Achievable bounds on signal transition activity. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , Roland W. Freund Circuit noise evaluation by Padé approximation based model-reduction techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard , Vinod Narayanan , Peter C. Elmendorf , Gutuan Zheng Global harmony: coupled noise analysis for full-chip RC interconnect networks. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan Efficient coupled noise estimation for on-chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. DeVane Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy R. Levitt , Kunle Olukotun Verifying correct pipeline implementation for microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Miodrag Potkonjak A quantitative approach to functional debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Kukimoto , Wilsin Gosti , Alexander Saldanha , Robert K. Brayton Approximate timing analysis of combinational circuits under the XBD0 model. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund Sivaraman , Andrzej J. Strojwas Timing analysis based on primitive path delay fault identification. [Citation Graph (0, 0)][DBLP ] Conf ] Supratik Chakraborty , David L. Dill Approximate algorithms for time separation of events. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Visweswariah Optimization techniques for high-performance digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Mehrotra , Shaz Qadeer , Vigyan Singhal , Robert K. Brayton , Adnan Aziz , Alberto L. Sangiovanni-Vincentelli Sequential optimisation without state space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh Maheshwari , Sachin S. Sapatnekar Minimum area retiming with equivalent initial states. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Enric Pastor , Alexandre Yakovlev Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP ] Conf ] Chuck Monahan , Forrest Brewer Scheduling and binding bounds for RT-level symbolic execution. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Tung Chen , Kayhan Küçükçakar High-level scheduling model and control synthesis for a broad range of design applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Lakshminarayana , Kamal S. Khouri , Niraj K. Jha Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Lieven Vandenberghe , Stephen P. Boyd , Abbas El Gamal Optimal wire and transistor sizing for circuits with non-tree topology. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gary Ellis , Lawrence T. Pileggi , Rob A. Rutenbar A hierarchical decomposition methodology for multistage clock circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Griffith , Michel S. Nakhla A new high-order absolutely-stable explicit numerical integration algorithm for the time-domain simulation of nonlinear circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew R. Conn , Ruud A. Haring , Chandramouli Visweswariah , Chai Wah Wu Circuit optimization via adjoint Lagrangians. [Citation Graph (0, 0)][DBLP ] Conf ] Tuyen V. Nguyen , Anirudh Devgan State transformation in event driven explicit simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Evguenii I. Goldberg , Tiziano Villa , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli A fast and robust exact algorithm for face embedding. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , LaNae J. Avra , Edward J. McCluskey An output encoding problem and a solution technique. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Fuhrer , Steven M. Nowick OPTIMIST: state minimization for optimal 2-level logic implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Bringmann , Wolfgang Rosenstiel Resource sharing in hierarchical synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Salil Raje , Reinaldo A. Bergamaschi Generalized resource sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau Exploiting off-chip memory access modes in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Morgan Enos , Scott Hauck , Majid Sarrafzadeh Replication for logic bipartitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Dutt , Halim Theny Partitioning around roadblocks: tackling constraints with intermediate relaxations. [Citation Graph (0, 0)][DBLP ] Conf ] Wray L. Buntine , Lixin Su , A. Richard Newton , Andrew Mayer Adaptive methods for netlist partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] C.-J. Richard Shi , Xiang-Dong Tan Symbolic analysis of large analog circuits with determinant decision diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Francky Leyn , Walter Daems , Georges G. E. Gielen , Willy M. C. Sansen A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. [Citation Graph (0, 0)][DBLP ] Conf ] Pramodchandran N. Variyam , Abhijit Chatterjee Test generation for comprehensive testing of linear analog circuits using transient response sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Narayan , Adrian J. Isles , Jawahar Jain , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Reachability analysis using partitioned-ROBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Dominik Stoffel , Wolfgang Kunz Record & play: a structural fixed point iteration for sequential circuit verification. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Iwashita , Tsuneo Nakata Forward model checking techniques oriented to buggy designs. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Huan Chiang , Sandeep K. Gupta BIST TPG for faults in system backplanes. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , Mikhail Baklashov A test synthesis technique using redundant register transfers. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Built-in test generation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vi Chi Chan , David Lewis Hierarchical partitioning for field-programmable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Y. Zien , Pak K. Chan , Martine D. F. Schlag Hybrid spectral/iterative partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Honching Peter Li , Sung Kyu Lim , Toshiyuki Shibuya , Dongmin Xu Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Kapur , David E. Long IES3: a fast integral equation solver for efficient 3-dimensional extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Mattan Kamon , Nuno Alexandre Marques , Jacob White FastPep: a fast parasitic extraction program for complex three-dimensional geometries. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjit Gharpurey , Srinath Hosur Transform domain techniques for efficient extraction of substrate parasitics. [Citation Graph (0, 0)][DBLP ] Conf ] Mark D. Spiller , A. Richard Newton EDA and the network. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , David Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo Interconnect design for deep submicron ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph N. Kozhaya , Farid N. Najm Accurate power estimation for large sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli , Enrico Macii , Massimo Poncino , Riccardo Scarsi Fast power estimation for deterministic input streams. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou A power modeling and characterization method for macrocells using structure information. [Citation Graph (0, 0)][DBLP ] Conf ] Gilberto Fernandes Marchioro , Jean-Marc Daveau , Ahmed Amine Jerraya Transformational partitioning for co-design of multiprocessor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Asawaree Kalavade , P. A. Subrahmanyam Hardware/software partitioning for multi-function systems. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Dick , Niraj K. Jha MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Majid Sarrafzadeh , Maogang Wang NRG: global and detailed placement. [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Sato Simulated quenching: a new placement method for module generation. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasa Rao Arikati , Ravi Varadarajan A signature based approach to regularity extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Haluk Konuk Fault simulation of interconnect opens in digital CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tzuhao Chen , Ibrahim N. Hajj GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman , W. Kent Fuchs A deductive technique for diagnosis of bridging faults. [Citation Graph (0, 0)][DBLP ] Conf ] Unni Narayanan , C. L. Liu Low power logic synthesis for XOR based circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , D. F. Wong An exact gate decomposition algorithm for low-power technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Luca P. Carloni , Patrick C. McGeer , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli Trace driven logic synthesis&mdashapplication to power minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Surendra Bommu Performance analysis of a system of communicating processes. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Ernst , Wei Ye Embedded program timing analysis based on path clustering and architecture classification. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent John Mooney III , Giovanni De Micheli Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. [Citation Graph (0, 0)][DBLP ] Conf ] Chris C. N. Chu , D. F. Wong A new approach to simultaneous buffer insertion and wire sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Youxin Gao , D. F. Wong Optimal shape function for a bi-directional wire under Elmore delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Lei He , Cheng-Kok Koh , David Zhigang Pan Global interconnect sizing and spacing with consideration of coupling capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Test generation for primitive path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal Fast identification of untestable delay faults using implications. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Tafertshofer , Andreas Ganz , Manfred Henftling A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. [Citation Graph (0, 0)][DBLP ] Conf ] Sergey Gavrilov , Alexey Glebov , Satyamurthy Pullela , S. C. Moore , Abhijit Dharchoudhury , Rajendran Panda , G. Vijayan , David Blaauw Library-less synthesis for static CMOS combinational logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Premal Buch , Amit Narayan , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Logic synthesis for large pass transistor circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jinan Lou , Amir H. Salek , Massoud Pedram An exact solution to simultaneous technology mapping and linear placement problem. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Hoon Lee , Chang-hoon Choi , Jeong-Taek Kong , Wong-Seong Lee , Jei-Hwan Yoo An efficient statistical analysis methodology and its application to high-density DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Székely , Márta Rencz Fast field solver-programs for thermal and electrostatic analysis of microsystem elements. [Citation Graph (0, 0)][DBLP ] Conf ] Rachid Helaihel , Kunle Olukotun Java as a specification language for hardware-software systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Z. Su , Wayne Wei-Ming Dai Post-route optimization for improved yield using a rubber-band wiring model. [Citation Graph (0, 0)][DBLP ] Conf ] Maggie Zhiwei Kang , Wayne Wei-Ming Dai , Tom Dillinger , David P. LaPotin Delay bounded buffered tree construction for timing driven floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Cheng-Kok Koh Interconnect layout optimization under higher-order RLC model. [Citation Graph (0, 0)][DBLP ] Conf ] Sying-Jyan Wang , Tsi-Ming Tsai Test and diagnosis of fault logic blocks in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Alexander Saldanha , Alexander Taubin Partial scan delay fault testing of asynchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas Maximum independent sets on transitive graphs and their applications in testing and CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Kurshan , Vladimir Levin , Marius Minea , Doron Peled , Hüsnü Yenigün Verifying hardware in its software context. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth S. Kundert Simulation methods for RF integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 