Conferences in DBLP
Hong Li , Venkataramanan Balakrishnan , Cheng-Kok Koh Stable and compact inductance modeling of 3-D interconnect structures. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Yiyu Shi , Lei He , David Smart A fast block structure preserving model order reduction for inverse inductance circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Salvador Ortiz , Roberto Suaya Fullwave volumetric Maxwell solver using conduction modes. [Citation Graph (0, 0)][DBLP ] Conf ] Murari Mani , Ashish Kumar Singh , Michael Orshansky Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Vaibhav Nawale , Thomas W. Chen Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsu Huang , Chia-Ming Chang , Yow-Tyng Nieh State re-encoding for peak current minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh H. Kulkarni , Dennis Sylvester , David Blaauw A statistical framework for post-silicon tuning through body bias clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Shinkai , Masanori Hashimoto , Atsushi Kurokawa , Takao Onoye A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoji Ye , Peng Li , Frank Liu Practical variation-aware interconnect delay and slew analysis for statistical timing verification. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Cline , Kaviraj Chopra , David Blaauw , Yu Cao Analysis and modeling of CD variation for statistical static timing. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Parkhurst , John A. Darringer , Bill Grundmann From single core to multi-core: preparing for a new exponential. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Mueller , Alberto Rosti , Sara Bocchio , Elvinia Riccobene , Patrizia Scandurra , Wim Dehaene , Yves Vanderperren UML for ESL design: basic principles, tools, and applications. [Citation Graph (0, 0)][DBLP ] Conf ] Leonard Lee , Li-C. Wang On bounding the delay of a critical path. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A delay fault model for at-speed fault simulation and test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Min Kuo , Yue-Lung Chang , Shih-Chieh Chang Efficient Boolean characteristic function for fast timed ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Shun-Yen Lu , Pei-Ying Hsieh , Jing-Jia Liou Exploring linear structures of critical path delay faults to reduce test efforts. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng Zhuo , Jiang Hu , Min Zhao , Kangsheng Chen Fast decap allocation based on algebraic multigrid. [Citation Graph (0, 0)][DBLP ] Conf ] Nestoras E. Evmorfopoulos , Dimitris P. Karampatzakis , Georgios I. Stamoulis Precise identification of the worst-case voltage drop conditions in power grid verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Shebaita , Dusan Petranovic , Yehea I. Ismail Importance of volume discretization of single and coupled interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Nahi H. Abdul Ghani , Farid N. Najm Handling inductance in early power grid verification. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon R. Chiu , Deshanand P. Singh , Valavan Manohararajah , Stephen Dean Brown Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Satrajit Chatterjee , Alan Mishchenko , Robert K. Brayton Factor cuts. [Citation Graph (0, 0)][DBLP ] Conf ] Abusaleh M. Jabir , Dhiraj K. Pradhan , Jimson Mathew An efficient technique for synthesis and optimization of polynomials in GF(2m [Citation Graph (0, 0)][DBLP ] Conf ] Yu Zhou , Danil Sokolov , Alexandre Yakovlev Cost-aware synthesis of asynchronous circuits based on partial acknowledgement. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan Lin , Hai Zhou , Chris Chu A revisit to floorplan optimization by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Tan Yan , Hiroshi Murata Fast wire length estimation by net bundling for block placement. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Spindler , Frank M. Johannes Fast and robust quadratic placement combined with an exact linear net model. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Chieh Chen , Zhe-Wei Jiang , Tien-Chang Hsu , Hsin-Chen Chen , Yao-Wen Chang A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Shi , Yiorgos Makris Testing delay faults in asynchronous handshake circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nisar Ahmed , Mohammad Tehranipoor , Vinay Jayaram A novel framework for faster-than-at-speed delay test considering IR-drop effects. [Citation Graph (0, 0)][DBLP ] Conf ] Mihir R. Choudhury , Quming Zhou , Kartik Mohanram Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Erkan Acar , Sule Ozev , Kevin B. Redmond Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Sari Onaissi , Farid N. Najm A linear-time approach for static timing analysis covering all process corners. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Praveen Ghanta , Sarma B. K. Vrudhula A framework for statistical timing analysis using non-linear delay and slew models. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Ramalingam , Gi-Joon Nam , Ashish Kumar Singh , Michael Orshansky , Sani R. Nassif , David Z. Pan An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kaviraj Chopra , Bo Zhai , David Blaauw , Dennis Sylvester A new statistical max operation for propagating skewness in statistical timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , G. Chen , Mahmut T. Kandemir , Mustafa Karaköy Cache miss clustering for banked memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Seok-Won Seong , Prabhat Mishra A bitmask-based code compression technique for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Jia Chen , Tei-Wei Kuo Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Sheldon , Rakesh Kumar , Roman L. Lysecky , Frank Vahid , Dean M. Tullsen Application-specific customization of parameterized FPGA soft-core processors. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolue Lai , Jaijeet S. Roychowdhury TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Little , Nicholas Seegmiller , David Walter , Chris J. Myers , Tomohiro Yoneda Verification of analog/mixed-signal circuits using labeled hybrid petri nets. [Citation Graph (0, 0)][DBLP ] Conf ] Ting Mei , Jaijeet S. Roychowdhury PPV-HB: harmonic balance for oscillator/PLL phase macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] Gennette Gill , John Hansen , Montek Singh Loop pipelining for high-throughput stream computation using self-timed rings. [Citation Graph (0, 0)][DBLP ] Conf ] Min Ni , Seda Ogrenci Memik Thermal-induced leakage power optimization by redundant resource allocation. [Citation Graph (0, 0)][DBLP ] Conf ] W.-L. Hung , Xiaoxia Wu , Yuan Xie Guaranteeing performance yield in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Singhal , Gwan S. Choi , Rabi N. Mahapatra Information theoretic approach to address delay and reliability in long on-chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Zhang , Ari Arapostathis , Sani R. Nassif , Michael Orshansky Analytical modeling of SRAM dynamic stability. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , Massoud Momeni , Alberto García Ortiz , Manfred Glesner A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Frank , Ruchir Puri , Dorel Toma Design and CAD challenges in 45nm CMOS and beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando De Bernardinis , Pierluigi Nuzzo , Alberto L. Sangiovanni-Vincentelli Robust system level design with analog platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Nuttorn Jangkrajarng , Lihong Zhang , Sambuddha Bhattacharya , Nathan Kohagen , C.-J. Richard Shi Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Yiu-Cheong Tam , Evangeline F. Y. Young , Chris C. N. Chu Analog placement with symmetry and other placement constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasan Murali , Paolo Meloni , Federico Angiolini , David Atienza , Salvatore Carta , Luca Benini , Giovanni De Micheli , Luigi Raffo Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP ] Conf ] Gunar Schirner , Rainer Dömer Fast and accurate transaction level models using result oriented modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Yeow Meng Chee , Charles J. Colbourn , Alan C. H. Ling Optimal memoryless encoding for low power off-chip data buses. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Dutt , Huan Ren , Fenghua Yuan , Vishal Suthar A network-flow approach to timing-driven incremental placement for ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu Timing-driven placement for heterogeneous field programmable gate array. [Citation Graph (0, 0)][DBLP ] Conf ] Wan-Ping Lee , Hung-Yi Liu , Yao-Wen Chang Voltage island aware floorplanning for power and timing optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Wong , Jacob R. Minz , Sung Kyu Lim Decoupling capacitor planning and sizing for noise and leakage reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , DiaaEldin Khalil , Yehea I. Ismail , Hai Zhou A timing dependent power estimation framework considering coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth S. Stevens , Florentin Dartu Algorithms for MIS vector generation and pruning. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Zhou , Yi Zhu , Yuanfang Hu , Ronald Graham , Mike Hutton , Chung-Kuan Cheng Timing model reduction for hierarchical timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sean X. Shi , Peng Yu , David Z. Pan A unified non-rectangular device and circuit simulation model for timing and power. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoyao Liang , David Brooks Microarchitecture parameter selection to optimize system performance under process variation. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Somsubhra Mondal , Seda Ogrenci Memik Thermal sensor allocation and placement for reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Priya Sundararajan , Aman Gayasen , Narayanan Vijaykrishnan , Tim Tuan Thermal characterization and optimization in platform FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Júlvez , Jordi Cortadella , Michael Kishinevsky Performance analysis of concurrent systems with early evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Labrecque Near-term industrial perspective of analog CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar Design automation for analog: the next generation of tool challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Trent McConaghy , Georges G. E. Gielen Automation in mixed-signal design: challenges and solutions in the wake of the nano era. [Citation Graph (0, 0)][DBLP ] Conf ] Min Pan , Chris C. N. Chu FastRoute: a step to integrate global routing into placement. [Citation Graph (0, 0)][DBLP ] Conf ] Devang Jariwala , John Lillis Trunk decomposition based global routing optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Müller Optimizing yield in global routing. [Citation Graph (0, 0)][DBLP ] Conf ] Minsik Cho , David Z. Pan , Hua Xiang , Ruchir Puri Wire density driven global routing for CMP variation and timing. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay V. Kumar , Chris H. Kim , Sachin S. Sapatnekar An analytical model for negative bias temperature instability. [Citation Graph (0, 0)][DBLP ] Conf ] Hossein Asadi , Mehdi Baradaran Tahoori Soft error derating computation in sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev R. Rao , David Blaauw , Dennis Sylvester Soft error reduction in combinational logic using gate resizing and flipflop selection. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Yi Liu , Chung-Wei Lin , Szu-Jui Chou , Wei-Ting Tu , Chih-Hung Liu , Yao-Wen Chang , Sy-Yen Kuo Current path analysis for electrostatic discharge protection. [Citation Graph (0, 0)][DBLP ] Conf ] Xiliang Zhong , Cheng-Zhong Xu System-wide energy minimization for real-time tasks: lower bound and approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Tongquan Wei , Piyush Mishra , Kaijie Wu , Han Liang Online task-scheduling for fault-tolerant low-energy real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dakai Zhu , Hakan Aydin Energy management for real-time embedded systems with reliability requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Wang , Lei Wang Exploiting soft redundancy for error-resilient on-chip memory design. [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Siddharth Garg System-level process-driven variability analysis for single and multiple voltage-frequency island systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Seda Ogrenci Memik Physical aware frequency selection for dynamic thermal management in multi-core systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanyuan Jiang , Shiyan Hu , Jiang Hu , Zhuo Li , Weiping Shi A new RLC buffer insertion algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Rupak Samanta , Ganesh Venkataraman , Jiang Hu Clock buffer polarity assignment for power noise reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Venkataraman , Zhuo Feng , Jiang Hu , Peng Li Combinatorial algorithms for fast clock mesh optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sheng-Chih Lin , Kaustav Banerjee An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. [Citation Graph (0, 0)][DBLP ] Conf ] Yonghong Yang , Changyun Zhu , Zhenyu (Peter) Gu , Li Shang , Robert P. Dick Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design. [Citation Graph (0, 0)][DBLP ] Conf ] Jung Hwan Choi , Aditya Bansal , Mesut Meterelliyoz , Jayathi Murthy , Kaushik Roy Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sungpack Hong , Sungjoo Yoo , HoonSang Jin , Kyu-Myung Choi , Jeong-Taek Kong , Soo-Kwan Eo Runtime distribution-aware dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Ilie I. Luican , Hongwei Zhu , Florin Balasa Formal model of data reuse analysis for hierarchical memory organizations. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Hsien Wu , Tei-Wei Kuo An adaptive two-level management for the flash translation layer in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Raj Varada , Mysore Sriram , Kris Chou , James Guzzo Design and integration methods for a multi-threaded dual core 65nm Xeon® processor. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Ampalam , Montek Singh Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens. [Citation Graph (0, 0)][DBLP ] Conf ] Swaroop Ghosh , Swarup Bhunia , Kaushik Roy A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. [Citation Graph (0, 0)][DBLP ] Conf ] H. Yao , S. Sinha , C. Chiang , X. Hong , Y. Cai Efficient process-hotspot detection using range pattern matching. [Citation Graph (0, 0)][DBLP ] Conf ] Kuang-Yao Lee , Ting-Chi Wang , Kai-Yuan Chao Post-routing redundant via insertion and line end extension with via density consideration. [Citation Graph (0, 0)][DBLP ] Conf ] Royce L. S. Ching , Evangeline F. Y. Young , Kevin C. K. Leung , Chris Chu Post-placement voltage island generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Bokor Prospects for emerging nanoelectronics in mainstream information processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Chen Carbon nanotubes for potential electronic and optoelectronic applications. [Citation Graph (0, 0)][DBLP ] Conf ] H.-S. Philip Wong , Jie Deng , Arash Hazeghi , Tejas Krishnamohan , Gordon C. Wan Carbon nanotube transistor circuits: models and tools for design and performance optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoping Tang , Xin Yuan Technology migration techniques for simplified layouts with restrictive design rules. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Puneet Sharma , Alexander Zelikovsky Fill for shallow trench isolation CMP. [Citation Graph (0, 0)][DBLP ] Conf ] Zhe-Wei Jiang , Yao-Wen Chang An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. [Citation Graph (0, 0)][DBLP ] Conf ] Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. [Citation Graph (0, 0)][DBLP ] Conf ] Marvin Tom , David Leong , Guy G. Lemieux Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Jia , Ranga Vemuri Studying a GALS FPGA architecture using a parameterized automatic design flow. [Citation Graph (0, 0)][DBLP ] Conf ] David Sheldon , Rakesh Kumar , Frank Vahid , Dean M. Tullsen , Roman L. Lysecky Conjoining soft-core FPGA processors. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Toi , Noritsugu Nakamura , Yoshinosuke Kato , Toru Awashima , Kazutoshi Wakabayashi , Li Jing High-level synthesis challenges and solutions for a dynamically reconfigurable processor. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yiping Fan , Wei Jiang Platform-based resource binding using a distributed register-file microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Frank Vahid , Walid A. Najjar A code refinement methodology for performance-improved synthesis from C. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Venkataramani , Seth Copen Goldstein Leveraging protocol knowledge in slack matching. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori Application-independent defect-tolerant crossbar nano-architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rachlin , John E. Savage Nanowire addressing with randomized-contact decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Wang , Wenrui Gong , Ryan Kastner On the use of Bloom filters for defect maps in nanocomputing. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Dhiman , Tajana Simunic Rosing Dynamic power management using machine learning. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Najibi , M. Salehi , Ali Afzali-Kusha , Massoud Pedram , Seid Mehdi Fakhraie , Hossein Pedram Dynamic voltage and frequency management based on variable update intervals for frequency setting. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Yuan , Sean Leventhal , Gang Qu Temperature-aware leakage minimization technique for real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daler N. Rakhmatov Energy budgeting for battery-powered sensors with a known task schedule. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Marco Murciano , Sergio Nocco , Stefano Quer Stepping forward with interpolants in unbounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] David Ward , Fabio Somenzi Decomposing image computation for symbolic reachability analysis using control flow information. [Citation Graph (0, 0)][DBLP ] Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan , Daron Vroon Automatic memory reductions for RTL model verification. [Citation Graph (0, 0)][DBLP ] Conf ] Malay K. Ganai , Aarti Gupta Accelerating high-level bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Joanna Ho , Lei He Simultaneous power and thermal integrity driven via stapling in 3D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] A. Fazzi , L. Magagni , M. De Dominicis , P. Zoffoli , Roberto Canegallo , Pier Luigi Rolandi , Alberto L. Sangiovanni-Vincentelli , Roberto Guerrieri Yield prediction for 3D capacitive interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Renshen Wang , Rui Shi , Chung-Kuan Cheng Layer minimization of escape routing in area array packaging. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Jayakumar , Sunil P. Khatri , Kanupriya Gulati , Alexander Sprintson Network coding for routability improvement in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard E. Boser From micro to nano: MEMS as an interface to the nano world. [Citation Graph (0, 0)][DBLP ] Conf ] Ann Witvrouw CMOS-MEMS integration: why, how and what? [Citation Graph (0, 0)][DBLP ] Conf ] Richard A. Kiehl Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Bulovi , Kevin Ryu , Charles Sodini , Ioannis Kymissis , Annie Wang , Ivan Nausieda , Akintunde Ibitayo Akinwande Molecular organic electronic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Conor F. Madigan , Vladimir Bulovic Organic electronic device modeling at the nanoscale. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard , Daniel N. Maynard Variability and yield improvement: rules, models, and characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Satrajit Chatterjee , Robert K. Brayton , Niklas Eén Improvements to combinational equivalence checking. [Citation Graph (0, 0)][DBLP ] Conf ] Hossein M. Sheini , Karem A. Sakallah SMT(CLU ): a step toward scalability in system verification. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaohui Fu , Sharad Malik Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. [Citation Graph (0, 0)][DBLP ] Conf ] Beth Isaksen , Valeria Bertacco Verification through the principle of least astonishment. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Feng , Peng Li Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh K. Tiwary , Rob A. Rutenbar Faster, parametric trajectory-based macromodels via localized linear reductions. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Shen Wang , Michael Orshansky Robust estimation of parametric yield under limited descriptions of uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Carmona , Jordi Cortadella , Yousuke Takada , Ferdinand Peper From molecular interactions to gates: a systematic approach. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsien Kuo , Jacob White A spectrally accurate integral equation solver for molecular surface electrostatics. [Citation Graph (0, 0)][DBLP ] Conf ] Michael T. Niemier , Michael Crocker , Xiaobo Sharon Hu , Marya Lieberman Using CAD to shape experiments in molecular QCA. [Citation Graph (0, 0)][DBLP ] Conf ] 